riscv/rocket-chip
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LFSR now a util

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This commit is contained in:
Henry Cook 2012-01-24 14:39:52 -08:00
parent 7f26fe2c44
commit aa3465699b
2 changed files with 13 additions and 5 deletions
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7
rocket/src/main/scala/nbdcache.scala
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@ -17,11 +17,8 @@ class RandomReplacementWayGen extends Component {
val way_en = Bits(width = NWAYS, dir = INPUT) val way_en = Bits(width = NWAYS, dir = INPUT)
val way_id = UFix(width = log2up(NWAYS), dir = OUTPUT) val way_id = UFix(width = log2up(NWAYS), dir = OUTPUT)
} }
val width = max(6,log2up(NWAYS)) //TODO: Actually limit selection based on which ways are allowed (io.ways_en)
val lfsr = Reg(resetVal = UFix(1, width)) if(NWAYS > 1) io.way_id := LFSR16(io.way_en.orR)
when (io.way_en.orR) { lfsr <== Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
//TODO: Actually limit selection based on which ways are available (io.ways_en)
if(NWAYS > 1) io.way_id := lfsr(log2up(NWAYS)-1,0).toUFix
else io.way_id := UFix(0) else io.way_id := UFix(0)
} }

11
rocket/src/main/scala/util.scala
View File

@ -56,6 +56,17 @@ object UFixToOH
} }
} }
object LFSR16
{
def apply(increment: Bool) =
{
val width = 16
val lfsr = Reg(resetVal = UFix(1, width))
when (increment) { lfsr <== Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
lfsr
}
}
class Mux1H(n: Int, w: Int) extends Component class Mux1H(n: Int, w: Int) extends Component
{ {
val io = new Bundle { val io = new Bundle {