From aa3465699bf88f164e7a9661abf08acba5cdb18b Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@s144.Millennium.Berkeley.EDU>
Date: Tue, 24 Jan 2012 14:39:52 -0800
Subject: [PATCH] LFSR now a util

---
 rocket/src/main/scala/nbdcache.scala |  7 ++-----
 rocket/src/main/scala/util.scala     | 11 +++++++++++
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index f803ac3a..c908d788 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -17,11 +17,8 @@ class RandomReplacementWayGen extends Component {
     val way_en = Bits(width = NWAYS, dir = INPUT)
     val way_id = UFix(width = log2up(NWAYS), dir = OUTPUT)
   }
-  val width = max(6,log2up(NWAYS))
-  val lfsr = Reg(resetVal = UFix(1, width))
-  when (io.way_en.orR) { lfsr <== Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
-  //TODO: Actually limit selection based on which ways are available (io.ways_en)
-  if(NWAYS > 1) io.way_id := lfsr(log2up(NWAYS)-1,0).toUFix 
+  //TODO: Actually limit selection based on which ways are allowed (io.ways_en)
+  if(NWAYS > 1) io.way_id := LFSR16(io.way_en.orR)
   else io.way_id := UFix(0)
 }
 
diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala
index 837af57a..04ef0382 100644
--- a/rocket/src/main/scala/util.scala
+++ b/rocket/src/main/scala/util.scala
@@ -56,6 +56,17 @@ object UFixToOH
   }
 }
 
+object LFSR16
+{
+  def apply(increment: Bool) =
+  {
+    val width = 16
+    val lfsr = Reg(resetVal = UFix(1, width))
+    when (increment) { lfsr <== Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)).toUFix }
+    lfsr
+  }
+}
+
 class Mux1H(n: Int, w: Int) extends Component
 {
   val io = new Bundle {