changes to imports after uncore refactor
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@ -3,7 +3,6 @@
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package rocket
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import Chisel._
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import uncore._
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import cde.{Parameters, Field}
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import junctions.{ParameterizedBundle, DecoupledHelper}
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@ -6,7 +6,7 @@ import Chisel._
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import Util._
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import Instructions._
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import cde.{Parameters, Field}
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import uncore._
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import uncore.devices._
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import junctions.AddrMap
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class MStatus extends Bundle {
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@ -3,8 +3,12 @@
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package rocket
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import Chisel._
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import uncore._
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import junctions._
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import uncore.tilelink._
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import uncore.agents._
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import uncore.coherence._
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import uncore.util._
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import uncore.constants._
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import cde.{Parameters, Field}
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import Util._
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@ -250,7 +254,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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addr_block = s2_req.addr(paddrBits-1, blockOffBits),
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addr_beat = s2_req.addr(blockOffBits-1, beatOffBits),
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data = Fill(beatWords, pstore1_storegen.data),
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wmask = pstore1_storegen.mask << (uncachedPutOffset << wordOffBits),
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wmask = Some(pstore1_storegen.mask << (uncachedPutOffset << wordOffBits)),
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alloc = Bool(false))
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val uncachedPutAtomicMessage = PutAtomic(
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client_xact_id = UInt(0),
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@ -1,8 +1,11 @@
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package rocket
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import Chisel._
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import uncore._
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import uncore.DmaRequest._
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import uncore.tilelink._
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import uncore.devices._
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import uncore.devices.DmaRequest._
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import uncore.agents._
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import uncore.util._
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import junctions.{ParameterizedBundle, AddrMap}
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import cde.Parameters
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@ -1,7 +1,7 @@
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package rocket
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import Chisel._
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import uncore._
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import uncore.tilelink._
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import Util._
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import cde.{Parameters, Field}
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@ -1,7 +1,9 @@
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package rocket
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import Chisel._
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import uncore._
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import uncore.agents._
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import uncore.tilelink._
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import uncore.util._
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import Util._
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import cde.{Parameters, Field}
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@ -3,8 +3,12 @@
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package rocket
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import Chisel._
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import uncore._
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import junctions._
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import uncore.tilelink._
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import uncore.coherence._
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import uncore.agents._
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import uncore.util._
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import uncore.constants._
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import cde.{Parameters, Field}
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import Util._
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@ -207,7 +211,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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addr_block = addr_block,
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addr_beat = addr_beat,
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data = beat_data,
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wmask = beat_mask,
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wmask = Some(beat_mask),
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alloc = Bool(false))
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val putAtomic_acquire = PutAtomic(
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@ -456,7 +460,7 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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new Acquire,
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nMSHRs + nIOMSHRs,
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outerDataBeats,
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(a: Acquire) => a.hasMultibeatData()))
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Some((a: Acquire) => a.hasMultibeatData())))
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val mem_finish_arb = Module(new Arbiter(new FinishToDst, nMSHRs + nIOMSHRs))
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val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
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val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs))
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@ -994,7 +998,9 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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metaWriteArb.io.in(0) <> mshrs.io.meta_write
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// probes and releases
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val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
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val releaseArb = Module(new LockingArbiter(
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new Release, 2, outerDataBeats,
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Some((r: Release) => r.hasMultibeatData())))
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io.mem.release <> releaseArb.io.out
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prober.io.req.valid := io.mem.probe.valid && !lrsc_valid
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@ -3,7 +3,8 @@
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package rocket
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import Chisel._
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import uncore._
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import uncore.agents._
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import uncore.constants._
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import Util._
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import cde.{Parameters, Field}
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@ -3,7 +3,9 @@
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package rocket
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import Chisel._
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import uncore._
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import uncore.tilelink._
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import uncore.constants._
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import uncore.agents.CacheName
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import Util._
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import cde.{Parameters, Field}
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@ -4,7 +4,9 @@ package rocket
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import Chisel._
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import junctions._
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import uncore._
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import uncore.devices._
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import uncore.agents.CacheName
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import uncore.constants._
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import Util._
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import cde.{Parameters, Field}
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@ -3,7 +3,9 @@
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package rocket
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import Chisel._
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import uncore._
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import uncore.tilelink._
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import uncore.agents._
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import uncore.devices._
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import Util._
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import cde.{Parameters, Field}
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@ -7,7 +7,8 @@ import Util._
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import junctions._
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import scala.math._
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import cde.{Parameters, Field}
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import uncore.PseudoLRU
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import uncore.agents.PseudoLRU
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import uncore.coherence._
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case object NTLBEntries extends Field[Int]
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