diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala
index 507fb45e..6b3cee53 100644
--- a/rocket/src/main/scala/arbiter.scala
+++ b/rocket/src/main/scala/arbiter.scala
@@ -3,7 +3,6 @@
 package rocket
 
 import Chisel._
-import uncore._
 import cde.{Parameters, Field}
 import junctions.{ParameterizedBundle, DecoupledHelper}
 
diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala
index d223b6b5..017a115e 100644
--- a/rocket/src/main/scala/csr.scala
+++ b/rocket/src/main/scala/csr.scala
@@ -6,7 +6,7 @@ import Chisel._
 import Util._
 import Instructions._
 import cde.{Parameters, Field}
-import uncore._
+import uncore.devices._
 import junctions.AddrMap
 
 class MStatus extends Bundle {
diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala
index 965d4946..f565e4b6 100644
--- a/rocket/src/main/scala/dcache.scala
+++ b/rocket/src/main/scala/dcache.scala
@@ -3,8 +3,12 @@
 package rocket
 
 import Chisel._
-import uncore._
 import junctions._
+import uncore.tilelink._
+import uncore.agents._
+import uncore.coherence._
+import uncore.util._
+import uncore.constants._
 import cde.{Parameters, Field}
 import Util._
 
@@ -250,7 +254,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
     addr_block = s2_req.addr(paddrBits-1, blockOffBits),
     addr_beat = s2_req.addr(blockOffBits-1, beatOffBits),
     data = Fill(beatWords, pstore1_storegen.data),
-    wmask = pstore1_storegen.mask << (uncachedPutOffset << wordOffBits),
+    wmask = Some(pstore1_storegen.mask << (uncachedPutOffset << wordOffBits)),
     alloc = Bool(false))
   val uncachedPutAtomicMessage = PutAtomic(
     client_xact_id = UInt(0),
diff --git a/rocket/src/main/scala/dma.scala b/rocket/src/main/scala/dma.scala
index a7fabc1e..ce1af0ed 100644
--- a/rocket/src/main/scala/dma.scala
+++ b/rocket/src/main/scala/dma.scala
@@ -1,8 +1,11 @@
 package rocket
 
 import Chisel._
-import uncore._
-import uncore.DmaRequest._
+import uncore.tilelink._
+import uncore.devices._
+import uncore.devices.DmaRequest._
+import uncore.agents._
+import uncore.util._
 import junctions.{ParameterizedBundle, AddrMap}
 import cde.Parameters
 
diff --git a/rocket/src/main/scala/frontend.scala b/rocket/src/main/scala/frontend.scala
index d696cada..4c9d3aaf 100644
--- a/rocket/src/main/scala/frontend.scala
+++ b/rocket/src/main/scala/frontend.scala
@@ -1,7 +1,7 @@
 package rocket
 
 import Chisel._
-import uncore._
+import uncore.tilelink._
 import Util._
 import cde.{Parameters, Field}
 
diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala
index df01dc34..f41995d2 100644
--- a/rocket/src/main/scala/icache.scala
+++ b/rocket/src/main/scala/icache.scala
@@ -1,7 +1,9 @@
 package rocket
 
 import Chisel._
-import uncore._
+import uncore.agents._
+import uncore.tilelink._
+import uncore.util._
 import Util._
 import cde.{Parameters, Field}
 
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 7b336d37..3602700a 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -3,8 +3,12 @@
 package rocket
 
 import Chisel._
-import uncore._
 import junctions._
+import uncore.tilelink._
+import uncore.coherence._
+import uncore.agents._
+import uncore.util._
+import uncore.constants._
 import cde.{Parameters, Field}
 import Util._
 
@@ -207,7 +211,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
     addr_block = addr_block,
     addr_beat = addr_beat,
     data = beat_data,
-    wmask = beat_mask,
+    wmask = Some(beat_mask),
     alloc = Bool(false))
 
   val putAtomic_acquire = PutAtomic(
@@ -453,10 +457,10 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
   val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
   val mem_req_arb = Module(new LockingArbiter(
-                                  new Acquire,
-                                  nMSHRs + nIOMSHRs,
-                                  outerDataBeats,
-                                  (a: Acquire) => a.hasMultibeatData()))
+                                new Acquire,
+                                nMSHRs + nIOMSHRs,
+                                outerDataBeats,
+                                Some((a: Acquire) => a.hasMultibeatData())))
   val mem_finish_arb = Module(new Arbiter(new FinishToDst, nMSHRs + nIOMSHRs))
   val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
   val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs))
@@ -994,7 +998,9 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
   metaWriteArb.io.in(0) <> mshrs.io.meta_write
 
   // probes and releases
-  val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData()))
+  val releaseArb = Module(new LockingArbiter(
+                                new Release, 2, outerDataBeats,
+                                Some((r: Release) => r.hasMultibeatData())))
   io.mem.release <> releaseArb.io.out
 
   prober.io.req.valid := io.mem.probe.valid && !lrsc_valid
diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala
index a8d4ea5c..3b98dc25 100644
--- a/rocket/src/main/scala/ptw.scala
+++ b/rocket/src/main/scala/ptw.scala
@@ -3,7 +3,8 @@
 package rocket
 
 import Chisel._
-import uncore._
+import uncore.agents._
+import uncore.constants._
 import Util._
 import cde.{Parameters, Field}
 
diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala
index b5802d48..e8e5e626 100644
--- a/rocket/src/main/scala/rocc.scala
+++ b/rocket/src/main/scala/rocc.scala
@@ -3,7 +3,9 @@
 package rocket
 
 import Chisel._
-import uncore._
+import uncore.tilelink._
+import uncore.constants._
+import uncore.agents.CacheName
 import Util._
 import cde.{Parameters, Field}
 
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 2ca94cba..a94bdfa4 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -4,7 +4,9 @@ package rocket
 
 import Chisel._
 import junctions._
-import uncore._
+import uncore.devices._
+import uncore.agents.CacheName
+import uncore.constants._
 import Util._
 import cde.{Parameters, Field}
 
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index fca46187..3ace692e 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -3,7 +3,9 @@
 package rocket
 
 import Chisel._
-import uncore._
+import uncore.tilelink._
+import uncore.agents._
+import uncore.devices._
 import Util._
 import cde.{Parameters, Field}
 
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index 5977ba53..3ca8e73f 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -7,7 +7,8 @@ import Util._
 import junctions._
 import scala.math._
 import cde.{Parameters, Field}
-import uncore.PseudoLRU
+import uncore.agents.PseudoLRU
+import uncore.coherence._
 
 case object NTLBEntries extends Field[Int]