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changes to imports after uncore refactor

This commit is contained in:
Howard Mao 2016-06-28 13:15:39 -07:00
parent c10691b616
commit a9e0a5e2df
12 changed files with 42 additions and 20 deletions

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@ -3,7 +3,6 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import junctions.{ParameterizedBundle, DecoupledHelper} import junctions.{ParameterizedBundle, DecoupledHelper}

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@ -6,7 +6,7 @@ import Chisel._
import Util._ import Util._
import Instructions._ import Instructions._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import uncore._ import uncore.devices._
import junctions.AddrMap import junctions.AddrMap
class MStatus extends Bundle { class MStatus extends Bundle {

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@ -3,8 +3,12 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._
import junctions._ import junctions._
import uncore.tilelink._
import uncore.agents._
import uncore.coherence._
import uncore.util._
import uncore.constants._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import Util._ import Util._
@ -250,7 +254,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
addr_block = s2_req.addr(paddrBits-1, blockOffBits), addr_block = s2_req.addr(paddrBits-1, blockOffBits),
addr_beat = s2_req.addr(blockOffBits-1, beatOffBits), addr_beat = s2_req.addr(blockOffBits-1, beatOffBits),
data = Fill(beatWords, pstore1_storegen.data), data = Fill(beatWords, pstore1_storegen.data),
wmask = pstore1_storegen.mask << (uncachedPutOffset << wordOffBits), wmask = Some(pstore1_storegen.mask << (uncachedPutOffset << wordOffBits)),
alloc = Bool(false)) alloc = Bool(false))
val uncachedPutAtomicMessage = PutAtomic( val uncachedPutAtomicMessage = PutAtomic(
client_xact_id = UInt(0), client_xact_id = UInt(0),

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@ -1,8 +1,11 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._ import uncore.tilelink._
import uncore.DmaRequest._ import uncore.devices._
import uncore.devices.DmaRequest._
import uncore.agents._
import uncore.util._
import junctions.{ParameterizedBundle, AddrMap} import junctions.{ParameterizedBundle, AddrMap}
import cde.Parameters import cde.Parameters

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@ -1,7 +1,7 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._ import uncore.tilelink._
import Util._ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -1,7 +1,9 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._ import uncore.agents._
import uncore.tilelink._
import uncore.util._
import Util._ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -3,8 +3,12 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._
import junctions._ import junctions._
import uncore.tilelink._
import uncore.coherence._
import uncore.agents._
import uncore.util._
import uncore.constants._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import Util._ import Util._
@ -207,7 +211,7 @@ class IOMSHR(id: Int)(implicit p: Parameters) extends L1HellaCacheModule()(p) {
addr_block = addr_block, addr_block = addr_block,
addr_beat = addr_beat, addr_beat = addr_beat,
data = beat_data, data = beat_data,
wmask = beat_mask, wmask = Some(beat_mask),
alloc = Bool(false)) alloc = Bool(false))
val putAtomic_acquire = PutAtomic( val putAtomic_acquire = PutAtomic(
@ -453,10 +457,10 @@ class MSHRFile(implicit p: Parameters) extends L1HellaCacheModule()(p) {
val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs)) val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs))
val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs)) val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs))
val mem_req_arb = Module(new LockingArbiter( val mem_req_arb = Module(new LockingArbiter(
new Acquire, new Acquire,
nMSHRs + nIOMSHRs, nMSHRs + nIOMSHRs,
outerDataBeats, outerDataBeats,
(a: Acquire) => a.hasMultibeatData())) Some((a: Acquire) => a.hasMultibeatData())))
val mem_finish_arb = Module(new Arbiter(new FinishToDst, nMSHRs + nIOMSHRs)) val mem_finish_arb = Module(new Arbiter(new FinishToDst, nMSHRs + nIOMSHRs))
val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs)) val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs))
val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs)) val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs))
@ -994,7 +998,9 @@ class HellaCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
metaWriteArb.io.in(0) <> mshrs.io.meta_write metaWriteArb.io.in(0) <> mshrs.io.meta_write
// probes and releases // probes and releases
val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, (r: Release) => r.hasMultibeatData())) val releaseArb = Module(new LockingArbiter(
new Release, 2, outerDataBeats,
Some((r: Release) => r.hasMultibeatData())))
io.mem.release <> releaseArb.io.out io.mem.release <> releaseArb.io.out
prober.io.req.valid := io.mem.probe.valid && !lrsc_valid prober.io.req.valid := io.mem.probe.valid && !lrsc_valid

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@ -3,7 +3,8 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._ import uncore.agents._
import uncore.constants._
import Util._ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -3,7 +3,9 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._ import uncore.tilelink._
import uncore.constants._
import uncore.agents.CacheName
import Util._ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -4,7 +4,9 @@ package rocket
import Chisel._ import Chisel._
import junctions._ import junctions._
import uncore._ import uncore.devices._
import uncore.agents.CacheName
import uncore.constants._
import Util._ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -3,7 +3,9 @@
package rocket package rocket
import Chisel._ import Chisel._
import uncore._ import uncore.tilelink._
import uncore.agents._
import uncore.devices._
import Util._ import Util._
import cde.{Parameters, Field} import cde.{Parameters, Field}

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@ -7,7 +7,8 @@ import Util._
import junctions._ import junctions._
import scala.math._ import scala.math._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import uncore.PseudoLRU import uncore.agents.PseudoLRU
import uncore.coherence._
case object NTLBEntries extends Field[Int] case object NTLBEntries extends Field[Int]