riscv/rocket-chip
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changes to imports after uncore refactor

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Howard Mao
2016-06-28 13:15:39 -07:00
parent c10691b616
commit a9e0a5e2df
12 changed files with 42 additions and 20 deletions
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8
rocket/src/main/scala/dcache.scala
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@ -3,8 +3,12 @@
package rocket
import Chisel._
import uncore._
import junctions._
import uncore.tilelink._
import uncore.agents._
import uncore.coherence._
import uncore.util._
import uncore.constants._
import cde.{Parameters, Field}
import Util._
@ -250,7 +254,7 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
addr_block = s2_req.addr(paddrBits-1, blockOffBits),
addr_beat = s2_req.addr(blockOffBits-1, beatOffBits),
data = Fill(beatWords, pstore1_storegen.data),
wmask = pstore1_storegen.mask << (uncachedPutOffset << wordOffBits),
wmask = Some(pstore1_storegen.mask << (uncachedPutOffset << wordOffBits)),
alloc = Bool(false))
val uncachedPutAtomicMessage = PutAtomic(
client_xact_id = UInt(0),