riscv/rocket-chip
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ahb: lower hsel when idle to save power

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This commit is contained in:
Wesley W. Terpstra 2016-12-15 14:24:39 -08:00
parent 16febe7e94
commit a9b264e582
4 changed files with 6 additions and 8 deletions
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2
src/main/scala/uncore/ahb/Bundles.scala
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@ -13,7 +13,7 @@ class AHBBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
// Flow control signals from the master // Flow control signals from the master
val hmastlock = Bool(OUTPUT) val hmastlock = Bool(OUTPUT)
val htrans = UInt(OUTPUT, width = params.transBits) val htrans = UInt(OUTPUT, width = params.transBits)
val hsel = Bool(OUTPUT) // on a master, drive this with true val hsel = Bool(OUTPUT)
val hready = Bool(OUTPUT) // on a master, drive this from readyout val hready = Bool(OUTPUT) // on a master, drive this from readyout
// Payload signals // Payload signals

1
src/main/scala/uncore/ahb/Protocol.scala
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@ -3,7 +3,6 @@
package uncore.ahb package uncore.ahb
import Chisel._ import Chisel._
import chisel3.util.{Irrevocable, IrrevocableIO}
object AHBParameters object AHBParameters
{ {

2
src/main/scala/uncore/ahb/Xbar.scala
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@ -22,7 +22,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
} }
// Require consistent bus widths // Require consistent bus widths
val port0 = node.edgesIn(0).slave val port0 = node.edgesOut(0).slave
node.edgesOut.foreach { edge => node.edgesOut.foreach { edge =>
val port = edge.slave val port = edge.slave
require (port.beatBytes == port0.beatBytes, require (port.beatBytes == port0.beatBytes,

9
src/main/scala/uncore/tilelink2/ToAHB.scala
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@ -6,7 +6,6 @@ import Chisel._
import chisel3.internal.sourceinfo.SourceInfo import chisel3.internal.sourceinfo.SourceInfo
import config._ import config._
import diplomacy._ import diplomacy._
import util.PositionalMultiQueue
import uncore.ahb._ import uncore.ahb._
import scala.math.{min, max} import scala.math.{min, max}
import AHBParameters._ import AHBParameters._
@ -119,7 +118,7 @@ class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends Laz
out.hmastlock := Bool(false) // for now out.hmastlock := Bool(false) // for now
out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY)) out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY))
out.hsel := Bool(true) out.hsel := a_valid || !a_first
out.hready := out.hreadyout out.hready := out.hreadyout
out.hwrite := a_hasData out.hwrite := a_hasData
out.haddr := a.bits.address | a_offset out.haddr := a.bits.address | a_offset
@ -134,8 +133,8 @@ object TLToAHB
{ {
// applied to the TL source node; y.node := TLToAHB()(x.node) // applied to the TL source node; y.node := TLToAHB()(x.node)
def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = { def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
val axi4 = LazyModule(new TLToAHB(combinational)) val ahb = LazyModule(new TLToAHB(combinational))
axi4.node := x ahb.node := x
axi4.node ahb.node
} }
} }