diff --git a/src/main/scala/uncore/ahb/Bundles.scala b/src/main/scala/uncore/ahb/Bundles.scala
index 5822ff74..caf6d307 100644
--- a/src/main/scala/uncore/ahb/Bundles.scala
+++ b/src/main/scala/uncore/ahb/Bundles.scala
@@ -13,7 +13,7 @@ class AHBBundle(params: AHBBundleParameters) extends AHBBundleBase(params)
   // Flow control signals from the master
   val hmastlock = Bool(OUTPUT)
   val htrans    = UInt(OUTPUT, width = params.transBits)
-  val hsel      = Bool(OUTPUT) // on a master, drive this with true
+  val hsel      = Bool(OUTPUT)
   val hready    = Bool(OUTPUT) // on a master, drive this from readyout
 
   // Payload signals
diff --git a/src/main/scala/uncore/ahb/Protocol.scala b/src/main/scala/uncore/ahb/Protocol.scala
index 4dbd9f78..ba7c6b28 100644
--- a/src/main/scala/uncore/ahb/Protocol.scala
+++ b/src/main/scala/uncore/ahb/Protocol.scala
@@ -3,7 +3,6 @@
 package uncore.ahb
 
 import Chisel._
-import chisel3.util.{Irrevocable, IrrevocableIO}
 
 object AHBParameters
 {
diff --git a/src/main/scala/uncore/ahb/Xbar.scala b/src/main/scala/uncore/ahb/Xbar.scala
index 41ccf55f..e3128a6d 100644
--- a/src/main/scala/uncore/ahb/Xbar.scala
+++ b/src/main/scala/uncore/ahb/Xbar.scala
@@ -22,7 +22,7 @@ class AHBFanout()(implicit p: Parameters) extends LazyModule {
     }
 
     // Require consistent bus widths
-    val port0 = node.edgesIn(0).slave
+    val port0 = node.edgesOut(0).slave
     node.edgesOut.foreach { edge =>
       val port = edge.slave
       require (port.beatBytes == port0.beatBytes,
diff --git a/src/main/scala/uncore/tilelink2/ToAHB.scala b/src/main/scala/uncore/tilelink2/ToAHB.scala
index bdc8b454..7ceb86f7 100644
--- a/src/main/scala/uncore/tilelink2/ToAHB.scala
+++ b/src/main/scala/uncore/tilelink2/ToAHB.scala
@@ -6,7 +6,6 @@ import Chisel._
 import chisel3.internal.sourceinfo.SourceInfo
 import config._
 import diplomacy._
-import util.PositionalMultiQueue
 import uncore.ahb._
 import scala.math.{min, max}
 import AHBParameters._
@@ -119,7 +118,7 @@ class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends Laz
 
     out.hmastlock := Bool(false) // for now
     out.htrans    := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY))
-    out.hsel      := Bool(true)
+    out.hsel      := a_valid || !a_first
     out.hready    := out.hreadyout
     out.hwrite    := a_hasData
     out.haddr     := a.bits.address | a_offset
@@ -134,8 +133,8 @@ object TLToAHB
 {
   // applied to the TL source node; y.node := TLToAHB()(x.node)
   def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
-    val axi4 = LazyModule(new TLToAHB(combinational))
-    axi4.node := x
-    axi4.node
+    val ahb = LazyModule(new TLToAHB(combinational))
+    ahb.node := x
+    ahb.node
   }
 }