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ahb: lower hsel when idle to save power

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This commit is contained in:
Wesley W. Terpstra
2016-12-15 14:24:39 -08:00
parent 16febe7e94
commit a9b264e582
4 changed files with 6 additions and 8 deletions
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9
src/main/scala/uncore/tilelink2/ToAHB.scala
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@ -6,7 +6,6 @@ import Chisel._
import chisel3.internal.sourceinfo.SourceInfo
import config._
import diplomacy._
import util.PositionalMultiQueue
import uncore.ahb._
import scala.math.{min, max}
import AHBParameters._
@ -119,7 +118,7 @@ class TLToAHB(combinational: Boolean = true)(implicit p: Parameters) extends Laz
out.hmastlock := Bool(false) // for now
out.htrans := Mux(a_valid, Mux(a_first, TRANS_NONSEQ, TRANS_SEQ), Mux(a_first, TRANS_IDLE, TRANS_BUSY))
out.hsel := Bool(true)
out.hsel := a_valid || !a_first
out.hready := out.hreadyout
out.hwrite := a_hasData
out.haddr := a.bits.address | a_offset
@ -134,8 +133,8 @@ object TLToAHB
{
// applied to the TL source node; y.node := TLToAHB()(x.node)
def apply(combinational: Boolean = true)(x: TLOutwardNode)(implicit p: Parameters, sourceInfo: SourceInfo): AHBOutwardNode = {
val axi4 = LazyModule(new TLToAHB(combinational))
axi4.node := x
axi4.node
val ahb = LazyModule(new TLToAHB(combinational))
ahb.node := x
ahb.node
}
}