riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

diplomacy: use new node style chaining

Browse Source
This commit is contained in:
Wesley W. Terpstra 2017-10-27 01:13:19 -07:00
parent 6aac658184
commit a954f020a9
19 changed files with 134 additions and 132 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

31
src/main/scala/amba/ahb/Test.scala
View File

@ -25,8 +25,7 @@ class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff))) val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff)))
val gpio = LazyModule(new RRTest0(0x100)) val gpio = LazyModule(new RRTest0(0x100))
model.node := fuzz.node xbar.node := TLToAHB(aFlow) := TLDelayer(0.1) := model.node := fuzz.node
xbar.node := TLToAHB(aFlow)(TLDelayer(0.1)(model.node))
ram.node := xbar.node ram.node := xbar.node
gpio.node := xbar.node gpio.node := xbar.node
@ -46,13 +45,13 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel("AHBFuzzMaster")) val model = LazyModule(new TLRAMModel("AHBFuzzMaster"))
model.node := fuzz.node (node
node := := TLToAHB(aFlow)
TLToAHB(aFlow)( := TLDelayer(0.2)
TLDelayer(0.2)( := TLBuffer(BufferParams.flow)
TLBuffer(BufferParams.flow)( := TLDelayer(0.2)
TLDelayer(0.2)( := model.node
model.node)))) := fuzz.node)
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle { val io = IO(new Bundle {
@ -68,13 +67,13 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule
val node = AHBIdentityNode() val node = AHBIdentityNode()
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff))) val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff)))
ram.node := (ram.node
TLFragmenter(4, 16)( := TLFragmenter(4, 16)
TLDelayer(0.2)( := TLDelayer(0.2)
TLBuffer(BufferParams.flow)( := TLBuffer(BufferParams.flow)
TLDelayer(0.2)( := TLDelayer(0.2)
AHBToTL()( := AHBToTL()
node))))) := node)
lazy val module = new LazyModuleImp(this) { } lazy val module = new LazyModuleImp(this) { }
} }

14
src/main/scala/amba/apb/Test.scala
View File

@ -24,15 +24,15 @@ class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L
val ram = LazyModule(new APBRAM(AddressSet(0x0, 0xff))) val ram = LazyModule(new APBRAM(AddressSet(0x0, 0xff)))
val gpio = LazyModule(new RRTest0(0x100)) val gpio = LazyModule(new RRTest0(0x100))
model.node := fuzz.node
ram.node := xbar.node ram.node := xbar.node
gpio.node := xbar.node gpio.node := xbar.node
xbar.node := (xbar.node
TLToAPB(aFlow)( := TLToAPB(aFlow)
TLDelayer(0.2)( := TLDelayer(0.2)
TLBuffer(BufferParams.flow)( := TLBuffer(BufferParams.flow)
TLDelayer(0.2)( := TLDelayer(0.2)
model.node)))) := model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

54
src/main/scala/amba/axi4/Test.scala
View File

@ -25,10 +25,9 @@ class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
val gpio = LazyModule(new RRTest1(0x400)) val gpio = LazyModule(new RRTest1(0x400))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node))) ram.node := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(true ) := TLFragmenter(4, 16) := xbar.node
ram.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(true )(TLFragmenter(4, 16)(xbar.node)))) gpio.node := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(false) := TLFragmenter(4, 16) := xbar.node
gpio.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(false)(TLFragmenter(4, 16)(xbar.node))))
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished
@ -48,10 +47,9 @@ class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
val gpio = LazyModule(new RRTest0(0x400)) val gpio = LazyModule(new RRTest0(0x400))
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node
xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node))) ram.node := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(false) := xbar.node
ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(false)(xbar.node))) gpio.node := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(true ) := xbar.node
gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(true )(xbar.node)))
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished
@ -73,15 +71,15 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with
val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr))) val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr)))
val model = LazyModule(new TLRAMModel("AXI4FuzzMaster")) val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
model.node := fuzz.node (node
node := := AXI4UserYanker()
AXI4UserYanker()( := AXI4Deinterleaver(64)
AXI4Deinterleaver(64)( := TLToAXI4()
TLToAXI4()( := TLDelayer(0.1)
TLDelayer(0.1)( := TLBuffer(BufferParams.flow)
TLBuffer(BufferParams.flow)( := TLDelayer(0.1)
TLDelayer(0.1)( := model.node
model.node)))))) := fuzz.node)
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle { val io = IO(new Bundle {
@ -99,19 +97,19 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar
val ram = LazyModule(new TLRAM(fuzzAddr)) val ram = LazyModule(new TLRAM(fuzzAddr))
val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256))) val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256)))
ram.node := TLFragmenter(4, 16)(xbar.node) ram.node := TLFragmenter(4, 16) := xbar.node
error.node := xbar.node error.node := xbar.node
xbar.node := (xbar.node
TLFIFOFixer()( := TLFIFOFixer()
TLDelayer(0.1)( := TLDelayer(0.1)
TLBuffer(BufferParams.flow)( := TLBuffer(BufferParams.flow)
TLDelayer(0.1)( := TLDelayer(0.1)
AXI4ToTL()( := AXI4ToTL()
AXI4UserYanker(Some(4))( := AXI4UserYanker(Some(4))
AXI4Fragmenter()( := AXI4Fragmenter()
AXI4IdIndexer(2)( := AXI4IdIndexer(2)
node)))))))) := node)
lazy val module = new LazyModuleImp(this) { } lazy val module = new LazyModuleImp(this) { }
} }

2
src/main/scala/coreplex/MemoryBus.scala
View File

@ -72,7 +72,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu
for (bank <- 0 until nBanksPerChannel) { for (bank <- 0 until nBanksPerChannel) {
val offset = (bank * nMemoryChannels) + channel val offset = (bank * nMemoryChannels) + channel
ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus } ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus }
mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask)))(out) mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask))) := out
} }
mbus mbus
} }

5
src/main/scala/coreplex/PeripheryBus.scala
View File

@ -24,17 +24,16 @@ case object PeripheryBusKey extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") { class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
def toFixedWidthSingleBeatSlave(widthBytes: Int) = { def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode) TLFragmenter(widthBytes, params.blockBytes) := outwardWWNode
} }
def toLargeBurstSlave(maxXferBytes: Int) = { def toLargeBurstSlave(maxXferBytes: Int) = {
TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode) TLFragmenter(params.beatBytes, maxXferBytes) := outwardBufNode
} }
val fromSystemBus: TLInwardNode = { val fromSystemBus: TLInwardNode = {
val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic)) val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
inwardBufNode := atomics.node inwardBufNode := atomics.node
atomics.node
} }
def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) { def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) {

46
src/main/scala/coreplex/Ports.scala
View File

@ -55,11 +55,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus {
val buffer = LazyModule(new AXI4Buffer) val buffer = LazyModule(new AXI4Buffer)
memBuses.map(_.toDRAMController).foreach { case node => memBuses.map(_.toDRAMController).foreach { case node =>
converter.node := node mem_axi4 := buffer.node := yank.node := trim.node := converter.node := node
trim.node := converter.node
yank.node := trim.node
buffer.node := yank.node
mem_axi4 := buffer.node
} }
} }
@ -97,13 +93,13 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus {
supportsRead = TransferSizes(1, params.maxXferBytes))), supportsRead = TransferSizes(1, params.maxXferBytes))),
beatBytes = params.beatBytes))) beatBytes = params.beatBytes)))
mmio_axi4 := (mmio_axi4
AXI4Buffer()( := AXI4Buffer()
AXI4UserYanker()( := AXI4UserYanker()
AXI4Deinterleaver(sbus.blockBytes)( := AXI4Deinterleaver(sbus.blockBytes)
AXI4IdIndexer(params.idBits)( := AXI4IdIndexer(params.idBits)
TLToAXI4()( := TLToAXI4()
sbus.toFixedWidthPorts))))) := sbus.toFixedWidthPorts)
} }
/** Common io name and methods for propagating or tying off the port bundle */ /** Common io name and methods for propagating or tying off the port bundle */
@ -132,13 +128,13 @@ trait HasSlaveAXI4Port extends HasSystemBus {
id = IdRange(0, 1 << params.idBits)))))) id = IdRange(0, 1 << params.idBits))))))
private val fifoBits = 1 private val fifoBits = 1
sbus.fromSyncPorts() := (sbus.fromSyncPorts()
TLWidthWidget(params.beatBytes)( := TLWidthWidget(params.beatBytes)
AXI4ToTL()( := AXI4ToTL()
AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))( := AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))
AXI4Fragmenter()( := AXI4Fragmenter()
AXI4IdIndexer(fifoBits)( := AXI4IdIndexer(fifoBits)
l2FrontendAXI4Node))))) := l2FrontendAXI4Node)
} }
/** Common io name and methods for propagating or tying off the port bundle */ /** Common io name and methods for propagating or tying off the port bundle */
@ -177,10 +173,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus {
supportsPutPartial = TransferSizes(1, sbus.blockBytes))), supportsPutPartial = TransferSizes(1, sbus.blockBytes))),
beatBytes = params.beatBytes))) beatBytes = params.beatBytes)))
mmio_tl := mmio_tl := TLBuffer() := TLSourceShrinker(1 << params.idBits) := sbus.toFixedWidthPorts
TLBuffer()(
TLSourceShrinker(1 << params.idBits)(
sbus.toFixedWidthPorts))
} }
/** Common io name and methods for propagating or tying off the port bundle */ /** Common io name and methods for propagating or tying off the port bundle */
@ -215,10 +208,7 @@ trait HasSlaveTLPort extends HasSystemBus {
name = "Front Port (TL)", name = "Front Port (TL)",
sourceId = IdRange(0, 1 << params.idBits)))))) sourceId = IdRange(0, 1 << params.idBits))))))
sbus.fromSyncPorts() := sbus.fromSyncPorts() := TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes) := l2FrontendTLNode
TLSourceShrinker(1 << params.sourceBits)(
TLWidthWidget(params.beatBytes)(
l2FrontendTLNode))
} }
/** Common io name and methods for propagating or tying off the port bundle */ /** Common io name and methods for propagating or tying off the port bundle */
@ -259,7 +249,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex
for (i <- 0 until channels) { for (i <- 0 until channels) {
val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes)) val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes))
sram.node := AXI4Buffer()(AXI4Fragmenter()(node)) sram.node := AXI4Buffer() := AXI4Fragmenter() := node
} }
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {

6
src/main/scala/devices/debug/Debug.scala
View File

@ -393,9 +393,9 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
val dmiXbar = LazyModule (new TLXbar()) val dmiXbar = LazyModule (new TLXbar())
val dmOuter = LazyModule( new TLDebugModuleOuter(device)) val dmOuter = LazyModule( new TLDebugModuleOuter(device))
val intnode: IntSyncOutwardNode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode val intnode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode
val dmiInnerNode = TLAsyncCrossingSource()(dmiXbar.node) val dmiInnerNode = TLAsyncCrossingSource() := dmiXbar.node
dmiXbar.node := dmi2tl.node dmiXbar.node := dmi2tl.node
dmOuter.dmiNode := dmiXbar.node dmOuter.dmiNode := dmiXbar.node
@ -1006,7 +1006,7 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici
val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents)) val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents))
val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1)) val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1))
val dmiNode: TLAsyncInwardNode = dmiXing.node val dmiNode = dmiXing.node
val tlNode = dmInner.tlNode val tlNode = dmInner.tlNode
dmInner.dmiNode := dmiXing.node dmInner.dmiNode := dmiXing.node

3
src/main/scala/devices/tilelink/TestRAM.scala
View File

@ -67,8 +67,7 @@ class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) exten
val model = LazyModule(new TLRAMModel("ZeroDelay")) val model = LazyModule(new TLRAMModel("ZeroDelay"))
val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node ram.node := TLDelayer(0.25) := model.node := fuzz.node
ram.node := TLDelayer(0.25)(model.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

4
src/main/scala/rocket/ScratchpadSlavePort.scala
View File

@ -122,7 +122,9 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
xbar.node := slaveNode xbar.node := slaveNode
xbarPorts.foreach { case (port, bytes) => xbarPorts.foreach { case (port, bytes) =>
port := TLFragmenter(bytes, cacheBlockBytes, earlyAck=true)(if (bytes == xBytes) xbar.node else TLWidthWidget(xBytes)(xbar.node)) (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=true))
++ (xBytes != bytes).option(TLWidthWidget(xBytes)))
.foldRight(xbar.node:TLOutwardNode)(_ := _)
} }
} }
} }

3
src/main/scala/tilelink/AsyncCrossing.scala
View File

@ -108,8 +108,7 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8))) val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8)))
val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
model.node := fuzz.node ram.node := island.crossTLIn := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node
ram.node := island.crossTLIn := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

9
src/main/scala/tilelink/AtomicAutomata.scala
View File

@ -284,8 +284,13 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
val model = LazyModule(new TLRAMModel("AtomicAutomata")) val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node (ram.node
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node)))) := TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLAtomicAutomata()
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

24
src/main/scala/tilelink/Fragmenter.scala
View File

@ -294,18 +294,18 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
val model = LazyModule(new TLRAMModel("Fragmenter")) val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node (ram.node
ram.node := := TLDelayer(0.1)
TLDelayer(0.1)( := TLBuffer(BufferParams.flow)
TLBuffer(BufferParams.flow)( := TLDelayer(0.1)
TLDelayer(0.1)( := TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)
TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)( := TLDelayer(0.1)
TLDelayer(0.1)( := TLBuffer(BufferParams.flow)
TLBuffer(BufferParams.flow)( := TLFragmenter(ramBeatBytes, maxSize/2)
TLFragmenter(ramBeatBytes, maxSize/2)( := TLDelayer(0.1)
TLDelayer(0.1)( := TLBuffer(BufferParams.flow)
TLBuffer(BufferParams.flow)( := model.node
model.node))))))))) := fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

11
src/main/scala/tilelink/Fuzzer.scala
View File

@ -234,12 +234,11 @@ class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
val xbar2= LazyModule(new TLXbar) val xbar2= LazyModule(new TLXbar)
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
model.node := fuzz.node xbar2.node := TLAtomicAutomata() := model.node := fuzz.node
xbar2.node := TLAtomicAutomata()(model.node) ram2.node := TLFragmenter(16, 256) := xbar2.node
ram2.node := TLFragmenter(16, 256)(xbar2.node) xbar.node := TLWidthWidget(16) := TLHintHandler() := xbar2.node
xbar.node := TLWidthWidget(16)(TLHintHandler()(xbar2.node)) ram.node := TLFragmenter(4, 256) := TLBuffer() := xbar.node
ram.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node)) gpio.node := TLFragmenter(4, 32) := TLBuffer() := xbar.node
gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node))
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

9
src/main/scala/tilelink/HintHandler.scala
View File

@ -105,8 +105,13 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel("HintHandler")) val model = LazyModule(new TLRAMModel("HintHandler"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node (ram.node
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node)))) := TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLHintHandler()
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

13
src/main/scala/tilelink/RationalCrossing.scala
View File

@ -118,8 +118,11 @@ class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameter
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel(name)) val model = LazyModule(new TLRAMModel(name))
model.node := fuzz.node (node
node := TLRationalCrossingSource()(TLDelayer(0.25)(model.node)) := TLRationalCrossingSource()
:= TLDelayer(0.25)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle { val io = IO(new Bundle {
@ -133,7 +136,11 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame
val node = TLRationalIdentityNode() val node = TLRationalIdentityNode()
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
ram.node := TLFragmenter(4, 256)(TLDelayer(0.25)(TLRationalCrossingSink(direction)(node))) (ram.node
:= TLFragmenter(4, 256)
:= TLDelayer(0.25)
:= TLRationalCrossingSink(direction)
:= node)
lazy val module = new LazyModuleImp(this) { } lazy val module = new LazyModuleImp(this) { }
} }

4
src/main/scala/tilelink/RegisterRouterTest.scala
View File

@ -260,7 +260,7 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
val rrtr = LazyModule(new RRTest0(0x400)) val rrtr = LazyModule(new RRTest0(0x400))
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node)) rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished
@ -275,7 +275,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
val rrtr = LazyModule(new RRTest1(0x400)) val rrtr = LazyModule(new RRTest1(0x400))
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node)) rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

3
src/main/scala/tilelink/SRAM.scala
View File

@ -89,8 +89,7 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends
val model = LazyModule(new TLRAMModel("SRAMSimple")) val model = LazyModule(new TLRAMModel("SRAMSimple"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node ram.node := TLDelayer(0.25) := model.node := fuzz.node
ram.node := TLDelayer(0.25)(model.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

14
src/main/scala/tilelink/WidthWidget.scala
View File

@ -202,12 +202,14 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter
val model = LazyModule(new TLRAMModel("WidthWidget")) val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node (ram.node
ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)( := TLDelayer(0.1)
if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) } := TLFragmenter(4, 256)
else { := TLWidthWidget(second)
TLWidthWidget(second)( := TLWidthWidget(first)
TLWidthWidget(first)(TLDelayer(0.1)(model.node)))})) := TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

9
src/main/scala/tilelink/Xbar.scala
View File

@ -256,11 +256,10 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
val model = LazyModule(new TLRAMModel("Xbar")) val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
model.node := fuzz.node xbar.node := TLDelayer(0.1) := model.node := fuzz.node
xbar.node := TLDelayer(0.1)(model.node)
(0 until nManagers) foreach { n => (0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node)) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
} }
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {
@ -277,13 +276,13 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
val fuzzers = (0 until nClients) map { n => val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns)) val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1)(fuzz.node) xbar.node := TLDelayer(0.1) := fuzz.node
fuzz fuzz
} }
(0 until nManagers) foreach { n => (0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node)) ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
} }
lazy val module = new LazyModuleImp(this) with UnitTestModule { lazy val module = new LazyModuleImp(this) with UnitTestModule {