From a954f020a94ee06123c0d708ab889c271071a067 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 27 Oct 2017 01:13:19 -0700 Subject: [PATCH] diplomacy: use new node style chaining --- src/main/scala/amba/ahb/Test.scala | 31 ++++++----- src/main/scala/amba/apb/Test.scala | 14 ++--- src/main/scala/amba/axi4/Test.scala | 54 +++++++++---------- src/main/scala/coreplex/MemoryBus.scala | 2 +- src/main/scala/coreplex/PeripheryBus.scala | 5 +- src/main/scala/coreplex/Ports.scala | 46 +++++++--------- src/main/scala/devices/debug/Debug.scala | 6 +-- src/main/scala/devices/tilelink/TestRAM.scala | 3 +- .../scala/rocket/ScratchpadSlavePort.scala | 4 +- src/main/scala/tilelink/AsyncCrossing.scala | 3 +- src/main/scala/tilelink/AtomicAutomata.scala | 9 +++- src/main/scala/tilelink/Fragmenter.scala | 24 ++++----- src/main/scala/tilelink/Fuzzer.scala | 11 ++-- src/main/scala/tilelink/HintHandler.scala | 9 +++- .../scala/tilelink/RationalCrossing.scala | 13 +++-- .../scala/tilelink/RegisterRouterTest.scala | 4 +- src/main/scala/tilelink/SRAM.scala | 3 +- src/main/scala/tilelink/WidthWidget.scala | 14 ++--- src/main/scala/tilelink/Xbar.scala | 11 ++-- 19 files changed, 134 insertions(+), 132 deletions(-) diff --git a/src/main/scala/amba/ahb/Test.scala b/src/main/scala/amba/ahb/Test.scala index 857ec063..40877721 100644 --- a/src/main/scala/amba/ahb/Test.scala +++ b/src/main/scala/amba/ahb/Test.scala @@ -25,8 +25,7 @@ class AHBFuzzNative(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L val ram = LazyModule(new AHBRAM(AddressSet(0x0, 0xff))) val gpio = LazyModule(new RRTest0(0x100)) - model.node := fuzz.node - xbar.node := TLToAHB(aFlow)(TLDelayer(0.1)(model.node)) + xbar.node := TLToAHB(aFlow) := TLDelayer(0.1) := model.node := fuzz.node ram.node := xbar.node gpio.node := xbar.node @@ -46,13 +45,13 @@ class AHBFuzzMaster(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel("AHBFuzzMaster")) - model.node := fuzz.node - node := - TLToAHB(aFlow)( - TLDelayer(0.2)( - TLBuffer(BufferParams.flow)( - TLDelayer(0.2)( - model.node)))) + (node + := TLToAHB(aFlow) + := TLDelayer(0.2) + := TLBuffer(BufferParams.flow) + := TLDelayer(0.2) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) { val io = IO(new Bundle { @@ -68,13 +67,13 @@ class AHBFuzzSlave()(implicit p: Parameters) extends LazyModule val node = AHBIdentityNode() val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff))) - ram.node := - TLFragmenter(4, 16)( - TLDelayer(0.2)( - TLBuffer(BufferParams.flow)( - TLDelayer(0.2)( - AHBToTL()( - node))))) + (ram.node + := TLFragmenter(4, 16) + := TLDelayer(0.2) + := TLBuffer(BufferParams.flow) + := TLDelayer(0.2) + := AHBToTL() + := node) lazy val module = new LazyModuleImp(this) { } } diff --git a/src/main/scala/amba/apb/Test.scala b/src/main/scala/amba/apb/Test.scala index 93d922a7..2d88c031 100644 --- a/src/main/scala/amba/apb/Test.scala +++ b/src/main/scala/amba/apb/Test.scala @@ -24,15 +24,15 @@ class APBFuzzBridge(aFlow: Boolean, txns: Int)(implicit p: Parameters) extends L val ram = LazyModule(new APBRAM(AddressSet(0x0, 0xff))) val gpio = LazyModule(new RRTest0(0x100)) - model.node := fuzz.node ram.node := xbar.node gpio.node := xbar.node - xbar.node := - TLToAPB(aFlow)( - TLDelayer(0.2)( - TLBuffer(BufferParams.flow)( - TLDelayer(0.2)( - model.node)))) + (xbar.node + := TLToAPB(aFlow) + := TLDelayer(0.2) + := TLBuffer(BufferParams.flow) + := TLDelayer(0.2) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/amba/axi4/Test.scala b/src/main/scala/amba/axi4/Test.scala index 0cb5d9d6..63c82e28 100644 --- a/src/main/scala/amba/axi4/Test.scala +++ b/src/main/scala/amba/axi4/Test.scala @@ -25,10 +25,9 @@ class AXI4LiteFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule val gpio = LazyModule(new RRTest1(0x400)) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) - model.node := fuzz.node - xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node))) - ram.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(true )(TLFragmenter(4, 16)(xbar.node)))) - gpio.node := AXI4UserYanker()(AXI4IdIndexer(0)(TLToAXI4(false)(TLFragmenter(4, 16)(xbar.node)))) + xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node + ram.node := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(true ) := TLFragmenter(4, 16) := xbar.node + gpio.node := AXI4UserYanker() := AXI4IdIndexer(0) := TLToAXI4(false) := TLFragmenter(4, 16) := xbar.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished @@ -48,10 +47,9 @@ class AXI4FullFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule val gpio = LazyModule(new RRTest0(0x400)) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) - model.node := fuzz.node - xbar.node := TLDelayer(0.1)(TLBuffer(BufferParams.flow)(TLDelayer(0.2)(model.node))) - ram.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(false)(xbar.node))) - gpio.node := AXI4Fragmenter()(AXI4Deinterleaver(16)(TLToAXI4(true )(xbar.node))) + xbar.node := TLDelayer(0.1) := TLBuffer(BufferParams.flow) := TLDelayer(0.2) := model.node := fuzz.node + ram.node := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(false) := xbar.node + gpio.node := AXI4Fragmenter() := AXI4Deinterleaver(16) := TLToAXI4(true ) := xbar.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished @@ -73,15 +71,15 @@ class AXI4FuzzMaster(txns: Int)(implicit p: Parameters) extends LazyModule with val fuzz = LazyModule(new TLFuzzer(txns, overrideAddress = Some(fuzzAddr))) val model = LazyModule(new TLRAMModel("AXI4FuzzMaster")) - model.node := fuzz.node - node := - AXI4UserYanker()( - AXI4Deinterleaver(64)( - TLToAXI4()( - TLDelayer(0.1)( - TLBuffer(BufferParams.flow)( - TLDelayer(0.1)( - model.node)))))) + (node + := AXI4UserYanker() + := AXI4Deinterleaver(64) + := TLToAXI4() + := TLDelayer(0.1) + := TLBuffer(BufferParams.flow) + := TLDelayer(0.1) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) { val io = IO(new Bundle { @@ -99,19 +97,19 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule with HasFuzzTar val ram = LazyModule(new TLRAM(fuzzAddr)) val error= LazyModule(new TLError(ErrorParams(Seq(AddressSet(0x1800, 0xff)), maxTransfer = 256))) - ram.node := TLFragmenter(4, 16)(xbar.node) + ram.node := TLFragmenter(4, 16) := xbar.node error.node := xbar.node - xbar.node := - TLFIFOFixer()( - TLDelayer(0.1)( - TLBuffer(BufferParams.flow)( - TLDelayer(0.1)( - AXI4ToTL()( - AXI4UserYanker(Some(4))( - AXI4Fragmenter()( - AXI4IdIndexer(2)( - node)))))))) + (xbar.node + := TLFIFOFixer() + := TLDelayer(0.1) + := TLBuffer(BufferParams.flow) + := TLDelayer(0.1) + := AXI4ToTL() + := AXI4UserYanker(Some(4)) + := AXI4Fragmenter() + := AXI4IdIndexer(2) + := node) lazy val module = new LazyModuleImp(this) { } } diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala index 2a2f5286..105f132b 100644 --- a/src/main/scala/coreplex/MemoryBus.scala +++ b/src/main/scala/coreplex/MemoryBus.scala @@ -72,7 +72,7 @@ trait HasMemoryBus extends HasSystemBus with HasPeripheryBus with HasInterruptBu for (bank <- 0 until nBanksPerChannel) { val offset = (bank * nMemoryChannels) + channel ForceFanout(a = true) { implicit p => in := sbus.toMemoryBus } - mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask)))(out) + mbus.fromCoherenceManager := TLFilter(TLFilter.Mmask(AddressSet(offset * memBusBlockBytes, mask))) := out } mbus } diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala index 49f0b25b..9faee504 100644 --- a/src/main/scala/coreplex/PeripheryBus.scala +++ b/src/main/scala/coreplex/PeripheryBus.scala @@ -24,17 +24,16 @@ case object PeripheryBusKey extends Field[PeripheryBusParams] class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") { def toFixedWidthSingleBeatSlave(widthBytes: Int) = { - TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode) + TLFragmenter(widthBytes, params.blockBytes) := outwardWWNode } def toLargeBurstSlave(maxXferBytes: Int) = { - TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode) + TLFragmenter(params.beatBytes, maxXferBytes) := outwardBufNode } val fromSystemBus: TLInwardNode = { val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic)) inwardBufNode := atomics.node - atomics.node } def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) { diff --git a/src/main/scala/coreplex/Ports.scala b/src/main/scala/coreplex/Ports.scala index ba46859a..08362edc 100644 --- a/src/main/scala/coreplex/Ports.scala +++ b/src/main/scala/coreplex/Ports.scala @@ -55,11 +55,7 @@ trait HasMasterAXI4MemPort extends HasMemoryBus { val buffer = LazyModule(new AXI4Buffer) memBuses.map(_.toDRAMController).foreach { case node => - converter.node := node - trim.node := converter.node - yank.node := trim.node - buffer.node := yank.node - mem_axi4 := buffer.node + mem_axi4 := buffer.node := yank.node := trim.node := converter.node := node } } @@ -97,13 +93,13 @@ trait HasMasterAXI4MMIOPort extends HasSystemBus { supportsRead = TransferSizes(1, params.maxXferBytes))), beatBytes = params.beatBytes))) - mmio_axi4 := - AXI4Buffer()( - AXI4UserYanker()( - AXI4Deinterleaver(sbus.blockBytes)( - AXI4IdIndexer(params.idBits)( - TLToAXI4()( - sbus.toFixedWidthPorts))))) + (mmio_axi4 + := AXI4Buffer() + := AXI4UserYanker() + := AXI4Deinterleaver(sbus.blockBytes) + := AXI4IdIndexer(params.idBits) + := TLToAXI4() + := sbus.toFixedWidthPorts) } /** Common io name and methods for propagating or tying off the port bundle */ @@ -132,13 +128,13 @@ trait HasSlaveAXI4Port extends HasSystemBus { id = IdRange(0, 1 << params.idBits)))))) private val fifoBits = 1 - sbus.fromSyncPorts() := - TLWidthWidget(params.beatBytes)( - AXI4ToTL()( - AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1)))( - AXI4Fragmenter()( - AXI4IdIndexer(fifoBits)( - l2FrontendAXI4Node))))) + (sbus.fromSyncPorts() + := TLWidthWidget(params.beatBytes) + := AXI4ToTL() + := AXI4UserYanker(Some(1 << (params.sourceBits - fifoBits - 1))) + := AXI4Fragmenter() + := AXI4IdIndexer(fifoBits) + := l2FrontendAXI4Node) } /** Common io name and methods for propagating or tying off the port bundle */ @@ -177,10 +173,7 @@ trait HasMasterTLMMIOPort extends HasSystemBus { supportsPutPartial = TransferSizes(1, sbus.blockBytes))), beatBytes = params.beatBytes))) - mmio_tl := - TLBuffer()( - TLSourceShrinker(1 << params.idBits)( - sbus.toFixedWidthPorts)) + mmio_tl := TLBuffer() := TLSourceShrinker(1 << params.idBits) := sbus.toFixedWidthPorts } /** Common io name and methods for propagating or tying off the port bundle */ @@ -215,10 +208,7 @@ trait HasSlaveTLPort extends HasSystemBus { name = "Front Port (TL)", sourceId = IdRange(0, 1 << params.idBits)))))) - sbus.fromSyncPorts() := - TLSourceShrinker(1 << params.sourceBits)( - TLWidthWidget(params.beatBytes)( - l2FrontendTLNode)) + sbus.fromSyncPorts() := TLSourceShrinker(1 << params.sourceBits) := TLWidthWidget(params.beatBytes) := l2FrontendTLNode } /** Common io name and methods for propagating or tying off the port bundle */ @@ -259,7 +249,7 @@ class SimAXIMem(channels: Int, forceSize: BigInt = 0)(implicit p: Parameters) ex for (i <- 0 until channels) { val sram = LazyModule(new AXI4RAM(AddressSet(0, size-1), beatBytes = config.beatBytes)) - sram.node := AXI4Buffer()(AXI4Fragmenter()(node)) + sram.node := AXI4Buffer() := AXI4Fragmenter() := node } lazy val module = new LazyModuleImp(this) { diff --git a/src/main/scala/devices/debug/Debug.scala b/src/main/scala/devices/debug/Debug.scala index 68f45745..99794b66 100644 --- a/src/main/scala/devices/debug/Debug.scala +++ b/src/main/scala/devices/debug/Debug.scala @@ -393,9 +393,9 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La val dmiXbar = LazyModule (new TLXbar()) val dmOuter = LazyModule( new TLDebugModuleOuter(device)) - val intnode: IntSyncOutwardNode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode + val intnode = IntSyncCrossingSource(alreadyRegistered = true) :*= dmOuter.intnode - val dmiInnerNode = TLAsyncCrossingSource()(dmiXbar.node) + val dmiInnerNode = TLAsyncCrossingSource() := dmiXbar.node dmiXbar.node := dmi2tl.node dmOuter.dmiNode := dmiXbar.node @@ -1006,7 +1006,7 @@ class TLDebugModuleInnerAsync(device: Device, getNComponents: () => Int)(implici val dmInner = LazyModule(new TLDebugModuleInner(device, getNComponents)) val dmiXing = LazyModule(new TLAsyncCrossingSink(depth=1)) - val dmiNode: TLAsyncInwardNode = dmiXing.node + val dmiNode = dmiXing.node val tlNode = dmInner.tlNode dmInner.dmiNode := dmiXing.node diff --git a/src/main/scala/devices/tilelink/TestRAM.scala b/src/main/scala/devices/tilelink/TestRAM.scala index adad547d..0bd6eb6d 100644 --- a/src/main/scala/devices/tilelink/TestRAM.scala +++ b/src/main/scala/devices/tilelink/TestRAM.scala @@ -67,8 +67,7 @@ class TLRAMZeroDelay(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) exten val model = LazyModule(new TLRAMModel("ZeroDelay")) val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) - model.node := fuzz.node - ram.node := TLDelayer(0.25)(model.node) + ram.node := TLDelayer(0.25) := model.node := fuzz.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 833dfa0c..a4f8bcdc 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -122,7 +122,9 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend { val xbar = LazyModule(new TLXbar) xbar.node := slaveNode xbarPorts.foreach { case (port, bytes) => - port := TLFragmenter(bytes, cacheBlockBytes, earlyAck=true)(if (bytes == xBytes) xbar.node else TLWidthWidget(xBytes)(xbar.node)) + (Seq(port, TLFragmenter(bytes, cacheBlockBytes, earlyAck=true)) + ++ (xBytes != bytes).option(TLWidthWidget(xBytes))) + .foldRight(xbar.node:TLOutwardNode)(_ := _) } } } diff --git a/src/main/scala/tilelink/AsyncCrossing.scala b/src/main/scala/tilelink/AsyncCrossing.scala index 9c927bb8..6dc65b0f 100644 --- a/src/main/scala/tilelink/AsyncCrossing.scala +++ b/src/main/scala/tilelink/AsyncCrossing.scala @@ -108,8 +108,7 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule { val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8))) val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) } - model.node := fuzz.node - ram.node := island.crossTLIn := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node)) + ram.node := island.crossTLIn := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/AtomicAutomata.scala b/src/main/scala/tilelink/AtomicAutomata.scala index eccc70ec..42a5d83f 100644 --- a/src/main/scala/tilelink/AtomicAutomata.scala +++ b/src/main/scala/tilelink/AtomicAutomata.scala @@ -284,8 +284,13 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule val model = LazyModule(new TLRAMModel("AtomicAutomata")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) - model.node := fuzz.node - ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node)))) + (ram.node + := TLFragmenter(4, 256) + := TLDelayer(0.1) + := TLAtomicAutomata() + := TLDelayer(0.1) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/Fragmenter.scala b/src/main/scala/tilelink/Fragmenter.scala index 2f651007..b15585ec 100644 --- a/src/main/scala/tilelink/Fragmenter.scala +++ b/src/main/scala/tilelink/Fragmenter.scala @@ -294,18 +294,18 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa val model = LazyModule(new TLRAMModel("Fragmenter")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) - model.node := fuzz.node - ram.node := - TLDelayer(0.1)( - TLBuffer(BufferParams.flow)( - TLDelayer(0.1)( - TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)( - TLDelayer(0.1)( - TLBuffer(BufferParams.flow)( - TLFragmenter(ramBeatBytes, maxSize/2)( - TLDelayer(0.1)( - TLBuffer(BufferParams.flow)( - model.node))))))))) + (ram.node + := TLDelayer(0.1) + := TLBuffer(BufferParams.flow) + := TLDelayer(0.1) + := TLFragmenter(ramBeatBytes, maxSize, earlyAck = true) + := TLDelayer(0.1) + := TLBuffer(BufferParams.flow) + := TLFragmenter(ramBeatBytes, maxSize/2) + := TLDelayer(0.1) + := TLBuffer(BufferParams.flow) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/Fuzzer.scala b/src/main/scala/tilelink/Fuzzer.scala index 55678fb8..c2c03656 100644 --- a/src/main/scala/tilelink/Fuzzer.scala +++ b/src/main/scala/tilelink/Fuzzer.scala @@ -234,12 +234,11 @@ class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule val xbar2= LazyModule(new TLXbar) val fuzz = LazyModule(new TLFuzzer(txns)) - model.node := fuzz.node - xbar2.node := TLAtomicAutomata()(model.node) - ram2.node := TLFragmenter(16, 256)(xbar2.node) - xbar.node := TLWidthWidget(16)(TLHintHandler()(xbar2.node)) - ram.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node)) - gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node)) + xbar2.node := TLAtomicAutomata() := model.node := fuzz.node + ram2.node := TLFragmenter(16, 256) := xbar2.node + xbar.node := TLWidthWidget(16) := TLHintHandler() := xbar2.node + ram.node := TLFragmenter(4, 256) := TLBuffer() := xbar.node + gpio.node := TLFragmenter(4, 32) := TLBuffer() := xbar.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/HintHandler.scala b/src/main/scala/tilelink/HintHandler.scala index b1a8529e..78003bbd 100644 --- a/src/main/scala/tilelink/HintHandler.scala +++ b/src/main/scala/tilelink/HintHandler.scala @@ -105,8 +105,13 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule { val model = LazyModule(new TLRAMModel("HintHandler")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) - model.node := fuzz.node - ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node)))) + (ram.node + := TLFragmenter(4, 256) + := TLDelayer(0.1) + := TLHintHandler() + := TLDelayer(0.1) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/RationalCrossing.scala b/src/main/scala/tilelink/RationalCrossing.scala index 0fe12219..9d935b68 100644 --- a/src/main/scala/tilelink/RationalCrossing.scala +++ b/src/main/scala/tilelink/RationalCrossing.scala @@ -118,8 +118,11 @@ class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameter val fuzz = LazyModule(new TLFuzzer(txns)) val model = LazyModule(new TLRAMModel(name)) - model.node := fuzz.node - node := TLRationalCrossingSource()(TLDelayer(0.25)(model.node)) + (node + := TLRationalCrossingSource() + := TLDelayer(0.25) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) { val io = IO(new Bundle { @@ -133,7 +136,11 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame val node = TLRationalIdentityNode() val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) - ram.node := TLFragmenter(4, 256)(TLDelayer(0.25)(TLRationalCrossingSink(direction)(node))) + (ram.node + := TLFragmenter(4, 256) + := TLDelayer(0.25) + := TLRationalCrossingSink(direction) + := node) lazy val module = new LazyModuleImp(this) { } } diff --git a/src/main/scala/tilelink/RegisterRouterTest.scala b/src/main/scala/tilelink/RegisterRouterTest.scala index a43e00f1..d7157c83 100644 --- a/src/main/scala/tilelink/RegisterRouterTest.scala +++ b/src/main/scala/tilelink/RegisterRouterTest.scala @@ -260,7 +260,7 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val rrtr = LazyModule(new RRTest0(0x400)) - rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node)) + rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished @@ -275,7 +275,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(txns)) val rrtr = LazyModule(new RRTest1(0x400)) - rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node)) + rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/SRAM.scala b/src/main/scala/tilelink/SRAM.scala index 9f77903a..a98a1d8e 100644 --- a/src/main/scala/tilelink/SRAM.scala +++ b/src/main/scala/tilelink/SRAM.scala @@ -89,8 +89,7 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends val model = LazyModule(new TLRAMModel("SRAMSimple")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) - model.node := fuzz.node - ram.node := TLDelayer(0.25)(model.node) + ram.node := TLDelayer(0.25) := model.node := fuzz.node lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/WidthWidget.scala b/src/main/scala/tilelink/WidthWidget.scala index b48b3ddd..3aca8dab 100644 --- a/src/main/scala/tilelink/WidthWidget.scala +++ b/src/main/scala/tilelink/WidthWidget.scala @@ -202,12 +202,14 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter val model = LazyModule(new TLRAMModel("WidthWidget")) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) - model.node := fuzz.node - ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)( - if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) } - else { - TLWidthWidget(second)( - TLWidthWidget(first)(TLDelayer(0.1)(model.node)))})) + (ram.node + := TLDelayer(0.1) + := TLFragmenter(4, 256) + := TLWidthWidget(second) + := TLWidthWidget(first) + := TLDelayer(0.1) + := model.node + := fuzz.node) lazy val module = new LazyModuleImp(this) with UnitTestModule { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/tilelink/Xbar.scala b/src/main/scala/tilelink/Xbar.scala index 4a800231..ca3f9dbf 100644 --- a/src/main/scala/tilelink/Xbar.scala +++ b/src/main/scala/tilelink/Xbar.scala @@ -256,11 +256,10 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM val model = LazyModule(new TLRAMModel("Xbar")) val xbar = LazyModule(new TLXbar) - model.node := fuzz.node - xbar.node := TLDelayer(0.1)(model.node) + xbar.node := TLDelayer(0.1) := model.node := fuzz.node (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) - ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node)) + ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new LazyModuleImp(this) with UnitTestModule { @@ -277,13 +276,13 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(txns)) - xbar.node := TLDelayer(0.1)(fuzz.node) + xbar.node := TLDelayer(0.1) := fuzz.node fuzz } (0 until nManagers) foreach { n => - val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) - ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node)) + val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) + ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node } lazy val module = new LazyModuleImp(this) with UnitTestModule {