riscv/rocket-chip
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diplomacy: use new node style chaining

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This commit is contained in:
Wesley W. Terpstra
2017-10-27 01:13:19 -07:00
parent 6aac658184
commit a954f020a9
19 changed files with 134 additions and 132 deletions
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24
src/main/scala/tilelink/Fragmenter.scala
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@ -294,18 +294,18 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node
ram.node :=
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLFragmenter(ramBeatBytes, maxSize/2)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
model.node)))))))))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished