riscv/rocket-chip
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diplomacy: use new node style chaining

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This commit is contained in:
Wesley W. Terpstra
2017-10-27 01:13:19 -07:00
parent 6aac658184
commit a954f020a9
19 changed files with 134 additions and 132 deletions
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3
src/main/scala/tilelink/AsyncCrossing.scala
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@ -108,8 +108,7 @@ class TLRAMAsyncCrossing(txns: Int)(implicit p: Parameters) extends LazyModule {
val island = LazyModule(new CrossingWrapper(AsynchronousCrossing(8)))
val ram = island { LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) }
model.node := fuzz.node
ram.node := island.crossTLIn := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
ram.node := island.crossTLIn := TLFragmenter(4, 256) := TLDelayer(0.1) := model.node := fuzz.node
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

9
src/main/scala/tilelink/AtomicAutomata.scala
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@ -284,8 +284,13 @@ class TLRAMAtomicAutomata(txns: Int)(implicit p: Parameters) extends LazyModule
val model = LazyModule(new TLRAMModel("AtomicAutomata"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node))))
(ram.node
:= TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLAtomicAutomata()
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

24
src/main/scala/tilelink/Fragmenter.scala
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@ -294,18 +294,18 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int, txns: Int)(implicit p: Pa
val model = LazyModule(new TLRAMModel("Fragmenter"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node
ram.node :=
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLDelayer(0.1)(
TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
TLFragmenter(ramBeatBytes, maxSize/2)(
TLDelayer(0.1)(
TLBuffer(BufferParams.flow)(
model.node)))))))))
(ram.node
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLDelayer(0.1)
:= TLFragmenter(ramBeatBytes, maxSize, earlyAck = true)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= TLFragmenter(ramBeatBytes, maxSize/2)
:= TLDelayer(0.1)
:= TLBuffer(BufferParams.flow)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

11
src/main/scala/tilelink/Fuzzer.scala
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@ -234,12 +234,11 @@ class TLFuzzRAM(txns: Int)(implicit p: Parameters) extends LazyModule
val xbar2= LazyModule(new TLXbar)
val fuzz = LazyModule(new TLFuzzer(txns))
model.node := fuzz.node
xbar2.node := TLAtomicAutomata()(model.node)
ram2.node := TLFragmenter(16, 256)(xbar2.node)
xbar.node := TLWidthWidget(16)(TLHintHandler()(xbar2.node))
ram.node := TLFragmenter(4, 256)(TLBuffer()(xbar.node))
gpio.node := TLFragmenter(4, 32)(TLBuffer()(xbar.node))
xbar2.node := TLAtomicAutomata() := model.node := fuzz.node
ram2.node := TLFragmenter(16, 256) := xbar2.node
xbar.node := TLWidthWidget(16) := TLHintHandler() := xbar2.node
ram.node := TLFragmenter(4, 256) := TLBuffer() := xbar.node
gpio.node := TLFragmenter(4, 32) := TLBuffer() := xbar.node
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

9
src/main/scala/tilelink/HintHandler.scala
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@ -105,8 +105,13 @@ class TLRAMHintHandler(txns: Int)(implicit p: Parameters) extends LazyModule {
val model = LazyModule(new TLRAMModel("HintHandler"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node))))
(ram.node
:= TLFragmenter(4, 256)
:= TLDelayer(0.1)
:= TLHintHandler()
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

13
src/main/scala/tilelink/RationalCrossing.scala
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@ -118,8 +118,11 @@ class TLRAMRationalCrossingSource(name: String, txns: Int)(implicit p: Parameter
val fuzz = LazyModule(new TLFuzzer(txns))
val model = LazyModule(new TLRAMModel(name))
model.node := fuzz.node
node := TLRationalCrossingSource()(TLDelayer(0.25)(model.node))
(node
:= TLRationalCrossingSource()
:= TLDelayer(0.25)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) {
val io = IO(new Bundle {
@ -133,7 +136,11 @@ class TLRAMRationalCrossingSink(direction: RationalDirection)(implicit p: Parame
val node = TLRationalIdentityNode()
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
ram.node := TLFragmenter(4, 256)(TLDelayer(0.25)(TLRationalCrossingSink(direction)(node)))
(ram.node
:= TLFragmenter(4, 256)
:= TLDelayer(0.25)
:= TLRationalCrossingSink(direction)
:= node)
lazy val module = new LazyModuleImp(this) { }
}

4
src/main/scala/tilelink/RegisterRouterTest.scala
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@ -260,7 +260,7 @@ class FuzzRRTest0(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val rrtr = LazyModule(new RRTest0(0x400))
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished
@ -275,7 +275,7 @@ class FuzzRRTest1(txns: Int)(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(txns))
val rrtr = LazyModule(new RRTest1(0x400))
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
rrtr.node := TLFragmenter(4, 32) := TLDelayer(0.1) := fuzz.node
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

3
src/main/scala/tilelink/SRAM.scala
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@ -89,8 +89,7 @@ class TLRAMSimple(ramBeatBytes: Int, txns: Int)(implicit p: Parameters) extends
val model = LazyModule(new TLRAMModel("SRAMSimple"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node
ram.node := TLDelayer(0.25)(model.node)
ram.node := TLDelayer(0.25) := model.node := fuzz.node
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

14
src/main/scala/tilelink/WidthWidget.scala
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@ -202,12 +202,14 @@ class TLRAMWidthWidget(first: Int, second: Int, txns: Int)(implicit p: Parameter
val model = LazyModule(new TLRAMModel("WidthWidget"))
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node
ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)(
if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) }
else {
TLWidthWidget(second)(
TLWidthWidget(first)(TLDelayer(0.1)(model.node)))}))
(ram.node
:= TLDelayer(0.1)
:= TLFragmenter(4, 256)
:= TLWidthWidget(second)
:= TLWidthWidget(first)
:= TLDelayer(0.1)
:= model.node
:= fuzz.node)
lazy val module = new LazyModuleImp(this) with UnitTestModule {
io.finished := fuzz.module.io.finished

11
src/main/scala/tilelink/Xbar.scala
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@ -256,11 +256,10 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
val model = LazyModule(new TLRAMModel("Xbar"))
val xbar = LazyModule(new TLXbar)
model.node := fuzz.node
xbar.node := TLDelayer(0.1)(model.node)
xbar.node := TLDelayer(0.1) := model.node := fuzz.node
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new LazyModuleImp(this) with UnitTestModule {
@ -277,13 +276,13 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(txns))
xbar.node := TLDelayer(0.1)(fuzz.node)
xbar.node := TLDelayer(0.1) := fuzz.node
fuzz
}
(0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256) := TLDelayer(0.1) := xbar.node
}
lazy val module = new LazyModuleImp(this) with UnitTestModule {