riscv/rocket-chip
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diplomacy: use new node style chaining

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This commit is contained in:
Wesley W. Terpstra
2017-10-28 11:34:16 -07:00
parent 6aac658184
commit a954f020a9
19 changed files with 134 additions and 132 deletions
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src/main/scala/coreplex/PeripheryBus.scala
+2 -3
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@@ -24,17 +24,16 @@ case object PeripheryBusKey extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "PeripheryBus") {
def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
TLFragmenter(widthBytes, params.blockBytes) := outwardWWNode
}
def toLargeBurstSlave(maxXferBytes: Int) = {
TLFragmenter(params.beatBytes, maxXferBytes)(outwardBufNode)
TLFragmenter(params.beatBytes, maxXferBytes) := outwardBufNode
}
val fromSystemBus: TLInwardNode = {
val atomics = LazyModule(new TLAtomicAutomata(arithmetic = params.arithmetic))
inwardBufNode := atomics.node
atomics.node
}
def toTile(name: Option[String] = None)(gen: Parameters => TLInwardNode) {