riscv/rocket-chip
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Periphery: test bench looks for "testram"

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This commit is contained in:
Wesley W. Terpstra 2016-09-16 17:47:20 -07:00
parent b5ce6150c7
commit a9382b3116
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocketchip/Periphery.scala
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@ -334,7 +334,7 @@ trait PeripheryTestRAM extends LazyModule {
val ramBase = 0x52000000
val ramSize = 0x1000
val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1)))
val sram = LazyModule(new TLRAM(AddressSet(ramBase, ramSize-1)) { override def name = "testram" })
sram.node := TLFragmenter(peripheryBus.node, 4, 256)
}