riscv/rocket-chip
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Give I$ RAMs consistent names

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This commit is contained in:
Andrew Waterman 2017-03-30 15:50:54 -07:00
parent 2720095b8e
commit a8a2ee711c
1 changed files with 2 additions and 2 deletions
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src/main/scala/rocket/ICache.scala
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@ -127,8 +127,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer)
} }
s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_) s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_)
for (i <- 0 until nWays) { val data_arrays = Seq.fill(nWays) { SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits))) }
val data_array = SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits))) for ((data_array, i) <- data_arrays zipWithIndex) {
val wen = tl_out.d.valid && repl_way === UInt(i) val wen = tl_out.d.valid && repl_way === UInt(i)
when (wen) { when (wen) {
val e_d = code.encode(tl_out.d.bits.data) val e_d = code.encode(tl_out.d.bits.data)