From a8a2ee711ce6012c834f2ce2cdca1e94fbc7e335 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 30 Mar 2017 15:50:54 -0700 Subject: [PATCH] Give I$ RAMs consistent names --- src/main/scala/rocket/ICache.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index 2540c9e1..0218d3ff 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -127,8 +127,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) } s1_any_tag_hit := s1_tag_hit.reduceLeft(_||_) && !s1_disparity.reduceLeft(_||_) - for (i <- 0 until nWays) { - val data_array = SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits))) + val data_arrays = Seq.fill(nWays) { SeqMem(nSets * refillCycles, Bits(width = code.width(rowBits))) } + for ((data_array, i) <- data_arrays zipWithIndex) { val wen = tl_out.d.valid && repl_way === UInt(i) when (wen) { val e_d = code.encode(tl_out.d.bits.data)