riscv/rocket-chip
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more correct handling of internal state

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This commit is contained in:
Henry Cook 2014-10-21 17:40:30 -07:00
parent 044b19dbc1
commit a891ba1d46
1 changed files with 13 additions and 12 deletions
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25
uncore/src/main/scala/cache.scala
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@ -459,11 +459,22 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
val pending_probes = Reg(init = co.dir().flush) val pending_probes = Reg(init = co.dir().flush)
val curr_p_id = co.dir().next(pending_probes) val curr_p_id = co.dir().next(pending_probes)
val next_coh_on_release = co.masterMetadataOnRelease(
c_rel.payload,
xact_internal.meta.coh,
c_rel.header.src)
val next_coh_on_grant = co.masterMetadataOnGrant(
c_gnt.payload,
xact_internal.meta.coh,
c_gnt.header.dst)
val is_uncached = co.messageIsUncached(xact) val is_uncached = co.messageIsUncached(xact)
val tag_match = xact_internal.tag_match val tag_match = xact_internal.tag_match
val needs_writeback = co.needsWriteback(xact_internal.meta.coh) val needs_writeback = co.needsWriteback(xact_internal.meta.coh)
val is_hit = co.isHit(xact, xact_internal.meta.coh) val is_hit = co.isHit(xact, xact_internal.meta.coh)
val needs_probes = co.requiresProbes(xact.a_type, xact_internal.meta.coh) val needs_probes = co.requiresProbes(xact.a_type, xact_internal.meta.coh)
//TODO: does allocate
val c_rel_had_data = Reg(init = Bool(false)) val c_rel_had_data = Reg(init = Bool(false))
val c_rel_was_voluntary = Reg(init = Bool(false)) val c_rel_was_voluntary = Reg(init = Bool(false))
val wb_buffer = Reg{xact.data.clone} val wb_buffer = Reg{xact.data.clone}
@ -535,7 +546,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits) io.meta_write.bits.idx := xact.addr(untagBits-1,blockOffBits)
io.meta_write.bits.way_en := xact_internal.way_en io.meta_write.bits.way_en := xact_internal.way_en
io.meta_write.bits.data.tag := xact.addr >> UInt(untagBits) io.meta_write.bits.data.tag := xact.addr >> UInt(untagBits)
io.meta_write.bits.data.coh := xact_internal.meta.coh io.meta_write.bits.data.coh := next_coh_on_grant
switch (state) { switch (state) {
is(s_idle) { is(s_idle) {
@ -558,11 +569,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
val _is_hit = co.isHit(xact, coh) val _is_hit = co.isHit(xact, coh)
val _needs_probes = co.requiresProbes(xact.a_type, coh) val _needs_probes = co.requiresProbes(xact.a_type, coh)
xact_internal := io.meta_resp.bits xact_internal := io.meta_resp.bits
test := UInt(0)
when(!_needs_writeback) {
// xact_internal.meta.coh := co.masterMetadataOnFlush
test := UInt(12)
}
when(_needs_probes) { when(_needs_probes) {
pending_probes := coh.sharers pending_probes := coh.sharers
release_count := co.dir().count(coh.sharers) release_count := co.dir().count(coh.sharers)
@ -591,12 +597,7 @@ class L2AcquireTracker(trackerId: Int, bankId: Int, innerId: String, outerId: St
// Handle releases, which may have data being written back // Handle releases, which may have data being written back
io.inner.release.ready := Bool(true) io.inner.release.ready := Bool(true)
when(io.inner.release.valid) { when(io.inner.release.valid) {
/* xact_internal.meta.coh := next_coh_on_release
xact_internal.meta.coh := co.masterMetadataOnRelease(
c_rel.payload,
xact_internal.meta.coh,
c_rel.header.src)
*/
when(co.messageHasData(c_rel.payload)) { when(co.messageHasData(c_rel.payload)) {
c_rel_had_data := Bool(true) c_rel_had_data := Bool(true)
when(tag_match) { when(tag_match) {