riscv/rocket-chip
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rocket: base trait for reporting ecc errors

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This commit is contained in:
Henry Cook 2017-09-20 18:49:46 -07:00
parent ffa3ab29ac
commit a887baa615
3 changed files with 10 additions and 2 deletions
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3
src/main/scala/rocket/DCache.scala
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@ -11,7 +11,8 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import TLMessages._
class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)
with CanHaveErrors {
val correctable = (cacheParams.tagECC.canCorrect || cacheParams.dataECC.canCorrect).option(Valid(UInt(width = paddrBits)))
val uncorrectable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
val bus = Valid(UInt(width = paddrBits))

4
src/main/scala/rocket/ICache.scala
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@ -36,7 +36,9 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
val addr = UInt(width = vaddrBits)
}
class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
with HasL1ICacheParameters
with CanHaveErrors {
val correctable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
}

5
src/main/scala/util/ECC.scala
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@ -173,3 +173,8 @@ class SECDEDTest extends Module
io.correctable := d.correctable
io.uncorrectable := d.uncorrectable
}
trait CanHaveErrors extends Bundle {
val correctable: Option[ValidIO[UInt]]
val uncorrectable: Option[ValidIO[UInt]]
}