rocket: base trait for reporting ecc errors

src/main/scala/rocket/DCache.scala

@@ -11,7 +11,8 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 import TLMessages._
 
-class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p) {
+class DCacheErrors(implicit p: Parameters) extends L1HellaCacheBundle()(p)
+    with CanHaveErrors {
   val correctable = (cacheParams.tagECC.canCorrect || cacheParams.dataECC.canCorrect).option(Valid(UInt(width = paddrBits)))
   val uncorrectable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
   val bus = Valid(UInt(width = paddrBits))

src/main/scala/rocket/ICache.scala

@@ -36,7 +36,9 @@ class ICacheReq(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICache
   val addr = UInt(width = vaddrBits)
 }
 
-class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p) with HasL1ICacheParameters {
+class ICacheErrors(implicit p: Parameters) extends CoreBundle()(p)
+    with HasL1ICacheParameters
+    with CanHaveErrors {
   val correctable = (cacheParams.tagECC.canDetect || cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
   val uncorrectable = (cacheParams.itimAddr.nonEmpty && cacheParams.dataECC.canDetect).option(Valid(UInt(width = paddrBits)))
 }

src/main/scala/util/ECC.scala

@@ -173,3 +173,8 @@ class SECDEDTest extends Module
   io.correctable := d.correctable
   io.uncorrectable := d.uncorrectable
 }
+
+trait CanHaveErrors extends Bundle {
+  val correctable: Option[ValidIO[UInt]]
+  val uncorrectable: Option[ValidIO[UInt]]
+}