riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

[rocket] compute D$ tag bits based upon # of arbiter ports

Browse Source
This commit is contained in:
Andrew Waterman 2016-08-09 13:08:00 -07:00
parent 2a5aeeae24
commit a857b08c59
5 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
chisel3

@ -1 +1 @@
Subproject commit ce42ef15128a626e723249ae7b129fb5a370fa9c Subproject commit 2a074c828ddd8e6c20fa21d618664d50120f3d7a

2
firrtl

@ -1 +1 @@
Subproject commit 3e2ff71db633315455a72b00fc277dda18aca317 Subproject commit 7cda3c2825daa97422548e2f0658623234ca0e95

2
rocket/src/main/scala/nbdcache.scala
View File

@ -51,7 +51,7 @@ abstract class L1HellaCacheBundle(implicit val p: Parameters) extends junctions.
trait HasCoreMemOp extends HasCoreParameters { trait HasCoreMemOp extends HasCoreParameters {
val addr = UInt(width = coreMaxAddrBits) val addr = UInt(width = coreMaxAddrBits)
val tag = Bits(width = coreDCacheReqTagBits) val tag = Bits(width = dcacheReqTagBits)
val cmd = Bits(width = M_SZ) val cmd = Bits(width = M_SZ)
val typ = Bits(width = MT_SZ) val typ = Bits(width = MT_SZ)
} }

5
rocket/src/main/scala/rocket.scala
View File

@ -27,7 +27,6 @@ case object MulUnroll extends Field[Int]
case object DivEarlyOut extends Field[Boolean] case object DivEarlyOut extends Field[Boolean]
case object CoreInstBits extends Field[Int] case object CoreInstBits extends Field[Int]
case object CoreDataBits extends Field[Int] case object CoreDataBits extends Field[Int]
case object CoreDCacheReqTagBits extends Field[Int]
case object NCustomMRWCSRs extends Field[Int] case object NCustomMRWCSRs extends Field[Int]
case object MtvecWritable extends Field[Boolean] case object MtvecWritable extends Field[Boolean]
case object MtvecInit extends Field[BigInt] case object MtvecInit extends Field[BigInt]
@ -57,7 +56,9 @@ trait HasCoreParameters extends HasAddrMapParameters {
val coreInstBytes = coreInstBits/8 val coreInstBytes = coreInstBits/8
val coreDataBits = xLen val coreDataBits = xLen
val coreDataBytes = coreDataBits/8 val coreDataBytes = coreDataBits/8
val coreDCacheReqTagBits = 7 + (2 + (if(!usingRoCC) 0 else 1)) val dcacheArbPorts = 1 + (if (usingVM) 1 else 0) + p(BuildRoCC).size
val coreDCacheReqTagBits = 6
val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)
val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
val vaddrBitsExtended = vpnBitsExtended + pgIdxBits val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
val coreMaxAddrBits = paddrBits max vaddrBitsExtended val coreMaxAddrBits = paddrBits max vaddrBitsExtended

1
rocket/src/main/scala/tile.scala
View File

@ -138,6 +138,7 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
core.io.ptw <> ptw.io.dpath core.io.ptw <> ptw.io.dpath
} }
require(dcPorts.size == core.dcacheArbPorts)
val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams)) val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
dcArb.io.requestor <> dcPorts dcArb.io.requestor <> dcPorts
dcache.cpu <> dcArb.io.mem dcache.cpu <> dcArb.io.mem