diff --git a/chisel3 b/chisel3
index ce42ef15..2a074c82 160000
--- a/chisel3
+++ b/chisel3
@@ -1 +1 @@
-Subproject commit ce42ef15128a626e723249ae7b129fb5a370fa9c
+Subproject commit 2a074c828ddd8e6c20fa21d618664d50120f3d7a
diff --git a/firrtl b/firrtl
index 3e2ff71d..7cda3c28 160000
--- a/firrtl
+++ b/firrtl
@@ -1 +1 @@
-Subproject commit 3e2ff71db633315455a72b00fc277dda18aca317
+Subproject commit 7cda3c2825daa97422548e2f0658623234ca0e95
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index 6f71db0c..0c281438 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -51,7 +51,7 @@ abstract class L1HellaCacheBundle(implicit val p: Parameters) extends junctions.
 
 trait HasCoreMemOp extends HasCoreParameters {
   val addr = UInt(width = coreMaxAddrBits)
-  val tag  = Bits(width = coreDCacheReqTagBits)
+  val tag  = Bits(width = dcacheReqTagBits)
   val cmd  = Bits(width = M_SZ)
   val typ  = Bits(width = MT_SZ)
 }
diff --git a/rocket/src/main/scala/rocket.scala b/rocket/src/main/scala/rocket.scala
index 949ba94b..4d3f1da9 100644
--- a/rocket/src/main/scala/rocket.scala
+++ b/rocket/src/main/scala/rocket.scala
@@ -27,7 +27,6 @@ case object MulUnroll extends Field[Int]
 case object DivEarlyOut extends Field[Boolean]
 case object CoreInstBits extends Field[Int]
 case object CoreDataBits extends Field[Int]
-case object CoreDCacheReqTagBits extends Field[Int]
 case object NCustomMRWCSRs extends Field[Int]
 case object MtvecWritable extends Field[Boolean]
 case object MtvecInit extends Field[BigInt]
@@ -57,7 +56,9 @@ trait HasCoreParameters extends HasAddrMapParameters {
   val coreInstBytes = coreInstBits/8
   val coreDataBits = xLen
   val coreDataBytes = coreDataBits/8
-  val coreDCacheReqTagBits = 7 + (2 + (if(!usingRoCC) 0 else 1))
+  val dcacheArbPorts = 1 + (if (usingVM) 1 else 0) + p(BuildRoCC).size
+  val coreDCacheReqTagBits = 6
+  val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)
   val vpnBitsExtended = vpnBits + (vaddrBits < xLen).toInt
   val vaddrBitsExtended = vpnBitsExtended + pgIdxBits
   val coreMaxAddrBits = paddrBits max vaddrBitsExtended
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 66b16553..675f0e64 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -138,6 +138,7 @@ class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
     core.io.ptw <> ptw.io.dpath
   }
 
+  require(dcPorts.size == core.dcacheArbPorts)
   val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
   dcArb.io.requestor <> dcPorts
   dcache.cpu <> dcArb.io.mem