riscv/rocket-chip
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make sure clocks and reset signals get intialized properly

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Howard Mao committed 2016-06-08 15:38:39 -07:00
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commit a809a1712a
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junctions
+1 -1
Submodule junctions updated: 4562d3c98e...546aaad8cf.
vsrc/rocketTestHarness.v
+1 -1
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@@ -62,7 +62,7 @@ module rocketTestHarness;
reg clk = 1'b0;
reg reset = 1'b1;
reg r_reset;
reg r_reset = 1'b1;
reg start = 1'b0;
always #`CLOCK_PERIOD clk = ~clk;