riscv/rocket-chip
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Don't declare Reg inside of when

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We haven't yet decided what the Chisel3 semantics for this will be.
This commit is contained in:
Andrew Waterman 2015-09-30 12:43:00 -07:00
parent 2f3d15675c
commit a7c908cb83
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/btb.scala
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@ -174,6 +174,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
}
val updateHit = r_btb_update.bits.prediction.valid
val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
val useUpdatePageHit = updatePageHit.orR
val doIdxPageRepl = !useUpdatePageHit
@ -196,7 +197,6 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete
when (r_btb_update.valid) {
assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target")
val nextRepl = Counter(!updateHit, entries)._1
val waddr =
if (updates_out_of_order) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl)
else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)