From a7c908cb8303fac9801293e394a804da72ab5145 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 30 Sep 2015 12:43:00 -0700 Subject: [PATCH] Don't declare Reg inside of when We haven't yet decided what the Chisel3 semantics for this will be. --- rocket/src/main/scala/btb.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/btb.scala b/rocket/src/main/scala/btb.scala index b0ab7b11..d687c22e 100644 --- a/rocket/src/main/scala/btb.scala +++ b/rocket/src/main/scala/btb.scala @@ -174,6 +174,7 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete } val updateHit = r_btb_update.bits.prediction.valid + val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1 val useUpdatePageHit = updatePageHit.orR val doIdxPageRepl = !useUpdatePageHit @@ -196,7 +197,6 @@ class BTB(updates_out_of_order: Boolean = false) extends Module with BTBParamete when (r_btb_update.valid) { assert(io.req.bits.addr === r_btb_update.bits.target, "BTB request != I$ target") - val nextRepl = Counter(!updateHit, entries)._1 val waddr = if (updates_out_of_order) Mux(updateHits.orR, OHToUInt(updateHits), nextRepl) else Mux(updateHit, r_btb_update.bits.prediction.bits.entry, nextRepl)