riscv/rocket-chip
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Support CSR atomics on all CSRs, not just STATUS

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This commit is contained in:
Andrew Waterman
2014-01-21 16:17:39 -08:00
parent 6ba2c1abe5
commit a7489920ce
2 changed files with 18 additions and 22 deletions
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4
rocket/src/main/scala/dpath.scala
View File

@@ -281,7 +281,9 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
// processor control regfile write
pcr.io.rw.addr := wb_reg_inst(31,20)
pcr.io.rw.cmd := io.ctrl.csr
pcr.io.rw.wdata := wb_reg_wdata
pcr.io.rw.wdata := Mux(io.ctrl.csr === CSR.S, pcr.io.rw.rdata | wb_reg_wdata,
Mux(io.ctrl.csr === CSR.C, pcr.io.rw.rdata & ~wb_reg_wdata,
wb_reg_wdata))
io.rocc.cmd.bits.inst := new RoCCInstruction().fromBits(wb_reg_inst)
io.rocc.cmd.bits.rs1 := wb_reg_wdata

36
rocket/src/main/scala/dpath_util.scala
View File

@@ -246,11 +246,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
when (wen) {
when (decoded_addr(CSRs.status)) {
val sr_wdata = Mux(io.rw.cmd === CSR.S, reg_status.toBits | wdata,
Mux(io.rw.cmd === CSR.C, reg_status.toBits & ~wdata,
wdata))
reg_status := new Status().fromBits(sr_wdata)
reg_status := new Status().fromBits(wdata)
reg_status.s64 := true
reg_status.u64 := true
reg_status.zero := 0
@@ -258,22 +254,20 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
if (conf.rocc.isEmpty) reg_status.er := false
if (!conf.fpu) reg_status.ef := false
}
when (io.rw.cmd != CSR.C && io.rw.cmd != CSR.S) {
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt }
when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt }
when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
}
when (decoded_addr(CSRs.fflags)) { reg_fflags := wdata }
when (decoded_addr(CSRs.frm)) { reg_frm := wdata }
when (decoded_addr(CSRs.fcsr)) { reg_fflags := wdata; reg_frm := wdata >> reg_fflags.getWidth }
when (decoded_addr(CSRs.epc)) { reg_epc := wdata(VADDR_BITS,0).toSInt }
when (decoded_addr(CSRs.evec)) { reg_evec := wdata(VADDR_BITS-1,0).toSInt }
when (decoded_addr(CSRs.count)) { reg_time := wdata.toUInt }
when (decoded_addr(CSRs.compare)) { reg_compare := wdata(31,0).toUInt; r_irq_timer := Bool(false) }
when (decoded_addr(CSRs.fromhost)) { when (reg_fromhost === UInt(0) || !host_pcr_req_fire) { reg_fromhost := wdata } }
when (decoded_addr(CSRs.tohost)) { when (reg_tohost === UInt(0) || host_pcr_req_fire) { reg_tohost := wdata } }
when (decoded_addr(CSRs.clear_ipi)){ r_irq_ipi := wdata(0) }
when (decoded_addr(CSRs.sup0)) { reg_sup0 := wdata }
when (decoded_addr(CSRs.sup1)) { reg_sup1 := wdata }
when (decoded_addr(CSRs.ptbr)) { reg_ptbr := Cat(wdata(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUInt }
when (decoded_addr(CSRs.stats)) { reg_stats := wdata(0) }
}
io.host.ipi_rep.ready := Bool(true)