update chisel and remove SRAM_READ_LATENCY

rocket/src/main/scala/consts.scala

@@ -210,8 +210,6 @@ object Constants
   val HAVE_RVC = Bool(false);
   val HAVE_FPU = Bool(false);
   val HAVE_VEC = Bool(false);
-
-  val SRAM_READ_LATENCY = 0;
 }
 
 }

rocket/src/main/scala/dcache.scala

@@ -258,8 +258,8 @@ class rocketDCacheDM(lines: Int) extends Component {
     ((state === s_resolve_miss) && r_req_flush);
 
   val tag_array = Mem4(lines, r_cpu_req_ppn);
-  tag_array.setReadLatency(SRAM_READ_LATENCY);
+  tag_array.setReadLatency(1);
-//   tag_array.setTarget('inst);
+  tag_array.setTarget('inst);
   val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
 
   // valid bit array
@@ -375,8 +375,8 @@ class rocketDCacheDM(lines: Int) extends Component {
       store_wmask));
 
   val data_array = Mem4(lines*4, data_wdata);
-  data_array.setReadLatency(SRAM_READ_LATENCY);
+  data_array.setReadLatency(1);
-//   data_array.setTarget('inst);
+  data_array.setTarget('inst);
   val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask);
   val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
   val r_resp_data = Reg(resp_data);

rocket/src/main/scala/dpath_util.scala

@@ -29,8 +29,10 @@ class rocketDpathBTB(entries: Int) extends Component
   val taglsb = (VADDR_BITS-idxlsb);
   
   val vb_array = Mem(entries, io.wen || io.clr, io.correct_pc4(idxmsb,idxlsb), !io.clr, resetVal = Bool(false)); 
-  val tag_target_array = Mem(entries, io.wen, io.correct_pc4(idxmsb,idxlsb), 
+  val tag_target_array = Mem4(entries, io.wen, io.correct_pc4(idxmsb,idxlsb), 
                               Cat(io.correct_pc4(VADDR_BITS-1,idxmsb+1), io.correct_target(VADDR_BITS-1,idxlsb)))
+  tag_target_array.setReadLatency(0);
+  tag_target_array.setTarget('inst);
   val is_val       = vb_array(io.current_pc4(idxmsb,idxlsb));
   val tag_target   = tag_target_array(io.current_pc4(idxmsb, idxlsb));
   
@@ -226,20 +228,12 @@ class rocketDpathRegfile extends Component
 {
   override val io = new ioRegfile();
 
-  // FIXME: remove the first "if" case once Mem4 C backend bug is fixed
-  if (SRAM_READ_LATENCY == 0) {
-    val regfile = Mem(32, io.w0.en && (io.w0.addr != UFix(0,5)), io.w0.addr, io.w0.data);  
-    io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
-    io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
-  }
-  else {
   val regfile = Mem4(32, io.w0.data);
   regfile.setReadLatency(0);
   regfile.setTarget('inst);
   regfile.write(io.w0.addr, io.w0.data, io.w0.en);
   io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
   io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
-  }
 }
 
 }

rocket/src/main/scala/icache.scala

@@ -86,7 +86,7 @@ class rocketICacheDM(lines: Int) extends Component {
   val tag_we = (state === s_refill_wait) && io.mem.resp_val;
 
   val tag_array = Mem4(lines, r_cpu_req_ppn);
-  tag_array.setReadLatency(SRAM_READ_LATENCY);
+  tag_array.setReadLatency(1);
   tag_array.setTarget('inst);
   val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
 
@@ -107,7 +107,7 @@ class rocketICacheDM(lines: Int) extends Component {
     Mux((state === s_refill_wait) || (state === s_refill),  Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
       io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
   val data_array = Mem4(lines*REFILL_CYCLES, io.mem.resp_data);
-  data_array.setReadLatency(SRAM_READ_LATENCY);
+  data_array.setReadLatency(1);
   data_array.setTarget('inst);
   val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
 

rocket/src/main/scala/nbdcache.scala

@@ -387,7 +387,7 @@ class ReplayUnit extends Component {
   val sdq_addr = Mux(sdq_ren_retry, rp.sdq_id, Mux(sdq_ren_new, io.replay.bits.sdq_id, sdq_alloc_id))
 
   val sdq = Mem4(NSDQ, io.sdq_enq.bits)
-  sdq.setReadLatency(SRAM_READ_LATENCY)
+  sdq.setReadLatency(1);
   sdq.setTarget('inst)
   val sdq_dout = sdq.rw(sdq_addr, io.sdq_enq.bits, sdq_wen, cs = sdq_ren || sdq_wen)
 
@@ -540,7 +540,7 @@ class MetaDataArray(lines: Int) extends Component {
   }
 
   val vd_array = Mem4(lines, Bits(width = 2))
-  vd_array.setReadLatency(SRAM_READ_LATENCY)
+  vd_array.setReadLatency(1);
   val vd_wdata2 = Cat(io.state_req.bits.data.valid, io.state_req.bits.data.dirty)
   vd_array.write(io.state_req.bits.idx, vd_wdata2, io.state_req.valid && io.state_req.bits.rw)
   val vd_wdata1 = Cat(io.req.bits.data.valid, io.req.bits.data.dirty)
@@ -551,7 +551,7 @@ class MetaDataArray(lines: Int) extends Component {
   val vd_conflict = io.state_req.valid && (io.req.bits.idx === io.state_req.bits.idx)
 
   val tag_array = Mem4(lines, io.resp.tag)
-  tag_array.setReadLatency(SRAM_READ_LATENCY)
+  tag_array.setReadLatency(1);
   tag_array.setTarget('inst)
   val tag_rdata = tag_array.rw(io.req.bits.idx, io.req.bits.data.tag, io.req.valid && io.req.bits.rw, cs = io.req.valid)
 
@@ -596,7 +596,7 @@ class DataArray(lines: Int) extends Component {
   val wmask = FillInterleaved(8, io.req.bits.wmask)
 
   val array = Mem4(lines*REFILL_CYCLES, io.resp)
-  array.setReadLatency(SRAM_READ_LATENCY)
+  array.setReadLatency(1);
   array.setTarget('inst)
   val addr = Cat(io.req.bits.idx, io.req.bits.offset)
   val rdata = array.rw(addr, io.req.bits.data, io.req.valid && io.req.bits.rw, wmask, cs = io.req.valid)