riscv/rocket-chip
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Allow WideCounter to not be reset

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This commit is contained in:
Andrew Waterman 2016-09-18 18:45:51 -07:00
parent aa956c0108
commit a49814c667
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/rocket/util.scala
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@ -127,16 +127,16 @@ object Split
} }
// a counter that clock gates most of its MSBs using the LSB carry-out // a counter that clock gates most of its MSBs using the LSB carry-out
case class WideCounter(width: Int, inc: UInt = UInt(1)) case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true)
{ {
private val isWide = width > 2*inc.getWidth private val isWide = width > 2*inc.getWidth
private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
private val small = Reg(init=UInt(0, smallWidth)) private val small = if (reset) Reg(init=UInt(0, smallWidth)) else Reg(UInt(width = smallWidth))
private val nextSmall = small +& inc private val nextSmall = small +& inc
small := nextSmall small := nextSmall
private val large = if (isWide) { private val large = if (isWide) {
val r = Reg(init=UInt(0, width - smallWidth)) val r = if (reset) Reg(init=UInt(0, width - smallWidth)) else Reg(UInt(width = width - smallWidth))
when (nextSmall(smallWidth)) { r := r + UInt(1) } when (nextSmall(smallWidth)) { r := r + UInt(1) }
r r
} else null } else null