diff --git a/src/main/scala/rocket/util.scala b/src/main/scala/rocket/util.scala
index 182c7ba9..e40da39a 100644
--- a/src/main/scala/rocket/util.scala
+++ b/src/main/scala/rocket/util.scala
@@ -127,16 +127,16 @@ object Split
 }
 
 // a counter that clock gates most of its MSBs using the LSB carry-out
-case class WideCounter(width: Int, inc: UInt = UInt(1))
+case class WideCounter(width: Int, inc: UInt = UInt(1), reset: Boolean = true)
 {
   private val isWide = width > 2*inc.getWidth
   private val smallWidth = if (isWide) inc.getWidth max log2Up(width) else width
-  private val small = Reg(init=UInt(0, smallWidth))
+  private val small = if (reset) Reg(init=UInt(0, smallWidth)) else Reg(UInt(width = smallWidth))
   private val nextSmall = small +& inc
   small := nextSmall
 
   private val large = if (isWide) {
-    val r = Reg(init=UInt(0, width - smallWidth))
+    val r = if (reset) Reg(init=UInt(0, width - smallWidth)) else Reg(UInt(width = width - smallWidth))
     when (nextSmall(smallWidth)) { r := r + UInt(1) }
     r
   } else null