riscv/rocket-chip
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Don't instantiate PTW when UseVM=false

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This commit is contained in:
Andrew Waterman 2016-03-25 14:17:25 -07:00
parent 27b3cca046
commit a4685a073f
2 changed files with 27 additions and 23 deletions
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2
rocket/src/main/scala/tile.scala
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@ -125,10 +125,12 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
require(uncachedPorts.size == nUncachedTileLinkPorts)
require(cachedPorts.size == nCachedTileLinkPorts)
if (p(UseVM)) {
val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
ptw.io.requestor <> ptwPorts
ptw.io.mem +=: dcPorts
core.io.ptw <> ptw.io.dpath
}
val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
dcArb.io.requestor <> dcPorts

4
rocket/src/main/scala/tlb.scala
View File

@ -137,7 +137,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val w_array = Mux(priv_s, sw_array.toBits & pum_ok, uw_array.toBits)
val x_array = Mux(priv_s, sx_array.toBits, ux_array.toBits)
val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
val bad_va =
if (vpnBits == vpnBitsExtended) Bool(false)
else io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
@ -174,6 +174,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
io.ptw.req.bits.store := r_req.store
io.ptw.req.bits.fetch := r_req.instruction
if (usingVM) {
when (io.req.fire() && tlb_miss) {
state := s_request
r_refill_tag := lookup_tag
@ -195,6 +196,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
when (io.ptw.resp.valid) {
state := s_ready
}
}
}
class DecoupledTLB(implicit p: Parameters) extends Module {