From a4685a073fe799fda5367f7fe151111ecb0248cb Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Fri, 25 Mar 2016 14:17:25 -0700
Subject: [PATCH] Don't instantiate PTW when UseVM=false

---
 rocket/src/main/scala/tile.scala | 10 ++++----
 rocket/src/main/scala/tlb.scala  | 40 +++++++++++++++++---------------
 2 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index 1c5926ac..f417c853 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -125,10 +125,12 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
   require(uncachedPorts.size == nUncachedTileLinkPorts)
   require(cachedPorts.size == nCachedTileLinkPorts)
 
-  val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
-  ptw.io.requestor <> ptwPorts
-  ptw.io.mem +=: dcPorts
-  core.io.ptw <> ptw.io.dpath
+  if (p(UseVM)) {
+    val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
+    ptw.io.requestor <> ptwPorts
+    ptw.io.mem +=: dcPorts
+    core.io.ptw <> ptw.io.dpath
+  }
 
   val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
   dcArb.io.requestor <> dcPorts
diff --git a/rocket/src/main/scala/tlb.scala b/rocket/src/main/scala/tlb.scala
index aff29c03..2c3fe123 100644
--- a/rocket/src/main/scala/tlb.scala
+++ b/rocket/src/main/scala/tlb.scala
@@ -137,7 +137,7 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
   val w_array = Mux(priv_s, sw_array.toBits & pum_ok, uw_array.toBits)
   val x_array = Mux(priv_s, sx_array.toBits, ux_array.toBits)
 
-  val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
+  val vm_enabled = Bool(usingVM) && io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
   val bad_va =
     if (vpnBits == vpnBitsExtended) Bool(false)
     else io.req.bits.vpn(vpnBits) =/= io.req.bits.vpn(vpnBits-1)
@@ -174,26 +174,28 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
   io.ptw.req.bits.store := r_req.store
   io.ptw.req.bits.fetch := r_req.instruction
 
-  when (io.req.fire() && tlb_miss) {
-    state := s_request
-    r_refill_tag := lookup_tag
-    r_refill_waddr := repl_waddr
-    r_req := io.req.bits
-  }
-  when (state === s_request) {
-    when (io.ptw.invalidate) {
+  if (usingVM) {
+    when (io.req.fire() && tlb_miss) {
+      state := s_request
+      r_refill_tag := lookup_tag
+      r_refill_waddr := repl_waddr
+      r_req := io.req.bits
+    }
+    when (state === s_request) {
+      when (io.ptw.invalidate) {
+        state := s_ready
+      }
+      when (io.ptw.req.ready) {
+        state := s_wait
+        when (io.ptw.invalidate) { state := s_wait_invalidate }
+      }
+    }
+    when (state === s_wait && io.ptw.invalidate) {
+      state := s_wait_invalidate
+    }
+    when (io.ptw.resp.valid) {
       state := s_ready
     }
-    when (io.ptw.req.ready) {
-      state := s_wait
-      when (io.ptw.invalidate) { state := s_wait_invalidate }
-    }
-  }
-  when (state === s_wait && io.ptw.invalidate) {
-    state := s_wait_invalidate
-  }
-  when (io.ptw.resp.valid) {
-    state := s_ready
   }
 }