riscv/rocket-chip
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Don't instantiate PTW when UseVM=false

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This commit is contained in:
Andrew Waterman
2016-03-25 14:17:25 -07:00
parent 27b3cca046
commit a4685a073f
2 changed files with 27 additions and 23 deletions
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10
rocket/src/main/scala/tile.scala
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@ -125,10 +125,12 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
require(uncachedPorts.size == nUncachedTileLinkPorts)
require(cachedPorts.size == nCachedTileLinkPorts)
val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
ptw.io.requestor <> ptwPorts
ptw.io.mem +=: dcPorts
core.io.ptw <> ptw.io.dpath
if (p(UseVM)) {
val ptw = Module(new PTW(ptwPorts.size)(dcacheParams))
ptw.io.requestor <> ptwPorts
ptw.io.mem +=: dcPorts
core.io.ptw <> ptw.io.dpath
}
val dcArb = Module(new HellaCacheArbiter(dcPorts.size)(dcacheParams))
dcArb.io.requestor <> dcPorts