riscv/rocket-chip
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add support for different TileLink and MIF data widths

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This commit is contained in:
Howard Mao 2015-10-13 12:46:23 -07:00
parent c2ad0b7dd4
commit a44e054c77
4 changed files with 12 additions and 5 deletions
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2
junctions

@ -1 +1 @@
Subproject commit 4145f066e8a528f033cf8ef27bcf16843061dd67 Subproject commit 70a5971a223380f9334105aa715ba38fad9ef5f2

2
src/main/scala/Configs.scala
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@ -49,7 +49,7 @@ class DefaultConfig extends ChiselConfig (
log2Up(site(NMemoryChannels))) log2Up(site(NMemoryChannels)))
case MIFDataBits => Dump("MEM_DATA_BITS", 128) case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits)) case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits) case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
case NASTIDataBits => site(MIFDataBits) case NASTIDataBits => site(MIFDataBits)
case NASTIAddrBits => site(PAddrBits) case NASTIAddrBits => site(PAddrBits)
case NASTIIdBits => site(MIFTagBits) case NASTIIdBits => site(MIFTagBits)

11
src/main/scala/RocketChip.scala
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@ -233,10 +233,17 @@ class OuterMemorySystem extends Module with TopLevelParameters {
val interconnect = Module(new NASTITopInterconnect) val interconnect = Module(new NASTITopInterconnect)
for ((bank, i) <- managerEndpoints.zipWithIndex) { for ((bank, i) <- managerEndpoints.zipWithIndex) {
val factor = params(TLDataBits) / params(MIFDataBits)
val outermostTLParams = outerTLParams.alterPartial({
case TLDataBeats => params(MIFDataBeats)
case TLDataBits => params(MIFDataBits)
})
val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams) val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
val conv = Module(new NASTIIOTileLinkIOConverter)(outerTLParams) val narrow = Module(new TileLinkIONarrower(factor))(outerTLParams)
val conv = Module(new NASTIIOTileLinkIOConverter)(outermostTLParams)
unwrap.io.in <> bank.outerTL unwrap.io.in <> bank.outerTL
conv.io.tl <> unwrap.io.out narrow.io.in <> unwrap.io.out
conv.io.tl <> narrow.io.out
interconnect.io.masters(i) <> conv.io.nasti interconnect.io.masters(i) <> conv.io.nasti
} }

2
uncore

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Subproject commit 30c1dfe7722486eccf41cd2e0153de638724039e Subproject commit 52e1e91c281a03cd7b2399a0a811ad124749c1c8