From a44e054c77cd23e2666890ddc15ecbf316c03642 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 13 Oct 2015 12:46:23 -0700
Subject: [PATCH] add support for different TileLink and MIF data widths

---
 junctions                       |  2 +-
 src/main/scala/Configs.scala    |  2 +-
 src/main/scala/RocketChip.scala | 11 +++++++++--
 uncore                          |  2 +-
 4 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/junctions b/junctions
index 4145f066..70a5971a 160000
--- a/junctions
+++ b/junctions
@@ -1 +1 @@
-Subproject commit 4145f066e8a528f033cf8ef27bcf16843061dd67
+Subproject commit 70a5971a223380f9334105aa715ba38fad9ef5f2
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index c0e41538..2f2044db 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -49,7 +49,7 @@ class DefaultConfig extends ChiselConfig (
                           log2Up(site(NMemoryChannels)))
       case MIFDataBits => Dump("MEM_DATA_BITS", 128)
       case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
-      case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
+      case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
       case NASTIDataBits => site(MIFDataBits)
       case NASTIAddrBits => site(PAddrBits)
       case NASTIIdBits => site(MIFTagBits)
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 1bd91885..92aec688 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -233,10 +233,17 @@ class OuterMemorySystem extends Module with TopLevelParameters {
   val interconnect = Module(new NASTITopInterconnect)
 
   for ((bank, i) <- managerEndpoints.zipWithIndex) {
+    val factor = params(TLDataBits) / params(MIFDataBits)
+    val outermostTLParams = outerTLParams.alterPartial({
+      case TLDataBeats => params(MIFDataBeats)
+      case TLDataBits => params(MIFDataBits)
+    })
     val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
-    val conv = Module(new NASTIIOTileLinkIOConverter)(outerTLParams)
+    val narrow = Module(new TileLinkIONarrower(factor))(outerTLParams)
+    val conv = Module(new NASTIIOTileLinkIOConverter)(outermostTLParams)
     unwrap.io.in <> bank.outerTL
-    conv.io.tl <> unwrap.io.out
+    narrow.io.in <> unwrap.io.out
+    conv.io.tl <> narrow.io.out
     interconnect.io.masters(i) <> conv.io.nasti
   }
 
diff --git a/uncore b/uncore
index 30c1dfe7..52e1e91c 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 30c1dfe7722486eccf41cd2e0153de638724039e
+Subproject commit 52e1e91c281a03cd7b2399a0a811ad124749c1c8