riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add support for different TileLink and MIF data widths

Browse Source
This commit is contained in:
Howard Mao
2015-10-13 12:46:23 -07:00
parent c2ad0b7dd4
commit a44e054c77
4 changed files with 12 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/main/scala/RocketChip.scala
View File

@ -233,10 +233,17 @@ class OuterMemorySystem extends Module with TopLevelParameters {
val interconnect = Module(new NASTITopInterconnect)
for ((bank, i) <- managerEndpoints.zipWithIndex) {
val factor = params(TLDataBits) / params(MIFDataBits)
val outermostTLParams = outerTLParams.alterPartial({
case TLDataBeats => params(MIFDataBeats)
case TLDataBits => params(MIFDataBits)
})
val unwrap = Module(new ClientTileLinkIOUnwrapper)(outerTLParams)
val conv = Module(new NASTIIOTileLinkIOConverter)(outerTLParams)
val narrow = Module(new TileLinkIONarrower(factor))(outerTLParams)
val conv = Module(new NASTIIOTileLinkIOConverter)(outermostTLParams)
unwrap.io.in <> bank.outerTL
conv.io.tl <> unwrap.io.out
narrow.io.in <> unwrap.io.out
conv.io.tl <> narrow.io.out
interconnect.io.masters(i) <> conv.io.nasti
}