riscv/rocket-chip
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add support for different TileLink and MIF data widths

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This commit is contained in:
Howard Mao
2015-10-13 12:46:23 -07:00
parent c2ad0b7dd4
commit a44e054c77
4 changed files with 12 additions and 5 deletions
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2
src/main/scala/Configs.scala
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@ -49,7 +49,7 @@ class DefaultConfig extends ChiselConfig (
log2Up(site(NMemoryChannels)))
case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFDataBeats => site(TLDataBits)*site(TLDataBeats)/site(MIFDataBits)
case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
case NASTIDataBits => site(MIFDataBits)
case NASTIAddrBits => site(PAddrBits)
case NASTIIdBits => site(MIFTagBits)