riscv/rocket-chip
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add clock override to tile constructor (#42)

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useful to have upstream so that tape-outs can construct
rocket-chip to have cores on different clocks without
forking rocket
This commit is contained in:
Colin Schmidt 2016-07-21 20:56:52 -04:00 committed by Andrew Waterman
parent c069e66056
commit a43ad522dc
1 changed files with 4 additions and 3 deletions
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7
rocket/src/main/scala/tile.scala
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@ -22,8 +22,8 @@ case class RoccParameters(
csrs: Seq[Int] = Nil,
useFPU: Boolean = false)
abstract class Tile(resetSignal: Bool = null)
(implicit p: Parameters) extends Module(_reset = resetSignal) {
abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null)
(implicit p: Parameters) extends Module(Option(clockSignal), Option(resetSignal)) {
val nCachedTileLinkPorts = p(NCachedTileLinkPorts)
val nUncachedTileLinkPorts = p(NUncachedTileLinkPorts)
val dcacheParams = p.alterPartial({ case CacheName => "L1D" })
@ -35,7 +35,8 @@ abstract class Tile(resetSignal: Bool = null)
}
}
class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(resetSignal)(p) {
class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null)
(implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) {
val buildRocc = p(BuildRoCC)
val usingRocc = !buildRocc.isEmpty
val nRocc = buildRocc.size