From a43ad522dcfb509c772f230d8445bc2009226c57 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Thu, 21 Jul 2016 20:56:52 -0400 Subject: [PATCH] add clock override to tile constructor (#42) useful to have upstream so that tape-outs can construct rocket-chip to have cores on different clocks without forking rocket --- rocket/src/main/scala/tile.scala | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 9f635663..66b16553 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -22,8 +22,8 @@ case class RoccParameters( csrs: Seq[Int] = Nil, useFPU: Boolean = false) -abstract class Tile(resetSignal: Bool = null) - (implicit p: Parameters) extends Module(_reset = resetSignal) { +abstract class Tile(clockSignal: Clock = null, resetSignal: Bool = null) + (implicit p: Parameters) extends Module(Option(clockSignal), Option(resetSignal)) { val nCachedTileLinkPorts = p(NCachedTileLinkPorts) val nUncachedTileLinkPorts = p(NUncachedTileLinkPorts) val dcacheParams = p.alterPartial({ case CacheName => "L1D" }) @@ -35,7 +35,8 @@ abstract class Tile(resetSignal: Bool = null) } } -class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(resetSignal)(p) { +class RocketTile(clockSignal: Clock = null, resetSignal: Bool = null) + (implicit p: Parameters) extends Tile(clockSignal, resetSignal)(p) { val buildRocc = p(BuildRoCC) val usingRocc = !buildRocc.isEmpty val nRocc = buildRocc.size