1
0

add BRAMSlave unittest

This commit is contained in:
Howard Mao 2016-06-15 20:05:49 -07:00
parent 377de06b72
commit a43a93b55c

View File

@ -592,6 +592,80 @@ class AtosConverterTest(implicit p: Parameters) extends UnitTest {
io.finished := frontend.io.finished && backend.io.finished io.finished := frontend.io.finished && backend.io.finished
} }
class BRAMSlaveDriver(implicit val p: Parameters) extends Module
with HasTileLinkParameters {
val io = new Bundle {
val mem = new ClientUncachedTileLinkIO
val start = Bool(INPUT)
val finished = Bool(OUTPUT)
}
val (s_idle :: s_pf_req :: s_pf_stall :: s_pf_resp ::
s_put_req :: s_put_stall :: s_put_resp ::
s_get_req :: s_get_stall :: s_get_resp ::
s_done :: Nil) = Enum(Bits(), 11)
val state = Reg(init = s_idle)
val pf_acquire = PutPrefetch(
client_xact_id = UInt(0),
addr_block = UInt(0))
val (put_beat, put_done) = Counter(
state === s_put_req && io.mem.acquire.ready, tlDataBeats)
val put_data = Fill(tlDataBits / tlBeatAddrBits, put_beat)
val put_acquire = PutBlock(
client_xact_id = UInt(0),
addr_block = UInt(0),
addr_beat = put_beat,
data = put_data)
val get_acquire = GetBlock(
client_xact_id = UInt(0),
addr_block = UInt(0))
val (get_beat, get_done) = Counter(
state === s_get_resp && io.mem.grant.valid, tlDataBeats)
val get_data = Fill(tlDataBits / tlBeatAddrBits, get_beat)
val (stall_cnt, stall_done) = Counter(
state === s_pf_stall || state === s_put_stall || state === s_get_stall, 4)
io.mem.acquire.valid := (state === s_pf_req) || (state === s_put_req) || (state === s_get_req)
io.mem.acquire.bits := MuxBundle(state, get_acquire, Seq(
s_pf_req -> pf_acquire,
s_put_req -> put_acquire))
io.mem.grant.ready := (state === s_pf_resp) || (state === s_put_resp) || (state === s_get_resp)
when (state === s_idle && io.start) { state := s_pf_req }
when (state === s_pf_req && io.mem.acquire.ready) { state := s_pf_stall }
when (state === s_pf_stall && stall_done) { state := s_pf_resp }
when (state === s_pf_resp && io.mem.grant.valid) { state := s_put_req }
when (state === s_put_req && io.mem.acquire.ready) { state := s_put_stall }
when (state === s_put_stall && stall_done) { state := s_put_req }
when (put_done) { state := s_put_resp }
when (state === s_put_resp && io.mem.grant.valid) { state := s_get_req }
when (state === s_get_req && io.mem.acquire.ready) { state := s_get_stall }
when (state === s_get_stall && stall_done) { state := s_get_resp }
when (state === s_get_resp && io.mem.grant.valid) { state := s_get_stall }
when (get_done) { state := s_done }
io.finished := (state === s_done)
assert(!io.mem.grant.valid || !io.mem.grant.bits.hasData() ||
io.mem.grant.bits.data === get_data,
"BRAMSlaveTest: data doesn't match")
}
class BRAMSlaveTest(implicit val p: Parameters) extends UnitTest
with HasTileLinkParameters {
val driver = Module(new BRAMSlaveDriver)
val bram = Module(new BRAMSlave(tlDataBeats))
driver.io.start := io.start
io.finished := driver.io.finished
bram.io <> driver.io.mem
}
class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) { class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
val tests = Seq( val tests = Seq(
Module(new MultiWidthFifoTest), Module(new MultiWidthFifoTest),
@ -599,7 +673,8 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
Module(new TileLinkToSmiConverterTest), Module(new TileLinkToSmiConverterTest),
Module(new AtosConverterTest), Module(new AtosConverterTest),
Module(new NastiMemoryDemuxTest), Module(new NastiMemoryDemuxTest),
Module(new HastiTest)) Module(new HastiTest),
Module(new BRAMSlaveTest))
val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3) val s_idle :: s_start :: s_wait :: Nil = Enum(Bits(), 3)
val state = Reg(init = s_idle) val state = Reg(init = s_idle)
@ -607,6 +682,10 @@ class UnitTestSuite(implicit p: Parameters) extends GroundTest()(p) {
when (state === s_idle) { state := s_start } when (state === s_idle) { state := s_start }
when (state === s_start) { state := s_wait } when (state === s_start) { state := s_wait }
tests.foreach { mod => mod.io.start := (state === s_start) } tests.zipWithIndex.foreach { case (mod, i) =>
mod.io.start := (state === s_start)
val timeout = Timer(1000, mod.io.start, mod.io.finished)
assert(!timeout, s"UnitTest $i timed out")
}
io.finished := tests.map(_.io.finished).reduce(_ && _) io.finished := tests.map(_.io.finished).reduce(_ && _)
} }