axi4: parameterized AXI master constraint for aligned access
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@ -52,6 +52,7 @@ case class AXI4SlavePortParameters(
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case class AXI4MasterParameters(
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id: IdRange = IdRange(0, 1),
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aligned: Boolean = false,
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nodePath: Seq[BaseNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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@ -12,7 +12,11 @@ import scala.math.{min, max}
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case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
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dFn = { case (1, _) =>
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// We must erase all client information, because we crush their source Ids
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Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(id = IdRange(0, 1 << idBits)))))
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val masters = Seq(
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AXI4MasterParameters(
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id = IdRange(0, 1 << idBits),
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aligned = true))
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Seq(AXI4MasterPortParameters(masters))
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},
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uFn = { case (1, Seq(AXI4SlavePortParameters(slaves, beatBytes))) =>
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val managers = slaves.zipWithIndex.map { case (s, id) =>
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