axi4: parameterized AXI master constraint for aligned access
This commit is contained in:
parent
673cf1fdb5
commit
a423f97844
@ -52,6 +52,7 @@ case class AXI4SlavePortParameters(
|
|||||||
|
|
||||||
case class AXI4MasterParameters(
|
case class AXI4MasterParameters(
|
||||||
id: IdRange = IdRange(0, 1),
|
id: IdRange = IdRange(0, 1),
|
||||||
|
aligned: Boolean = false,
|
||||||
nodePath: Seq[BaseNode] = Seq())
|
nodePath: Seq[BaseNode] = Seq())
|
||||||
{
|
{
|
||||||
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
|
val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
|
||||||
|
@ -12,7 +12,11 @@ import scala.math.{min, max}
|
|||||||
case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
|
case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
|
||||||
dFn = { case (1, _) =>
|
dFn = { case (1, _) =>
|
||||||
// We must erase all client information, because we crush their source Ids
|
// We must erase all client information, because we crush their source Ids
|
||||||
Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(id = IdRange(0, 1 << idBits)))))
|
val masters = Seq(
|
||||||
|
AXI4MasterParameters(
|
||||||
|
id = IdRange(0, 1 << idBits),
|
||||||
|
aligned = true))
|
||||||
|
Seq(AXI4MasterPortParameters(masters))
|
||||||
},
|
},
|
||||||
uFn = { case (1, Seq(AXI4SlavePortParameters(slaves, beatBytes))) =>
|
uFn = { case (1, Seq(AXI4SlavePortParameters(slaves, beatBytes))) =>
|
||||||
val managers = slaves.zipWithIndex.map { case (s, id) =>
|
val managers = slaves.zipWithIndex.map { case (s, id) =>
|
||||||
|
Loading…
Reference in New Issue
Block a user