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axi4: parameterized AXI master constraint for aligned access

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This commit is contained in:
Wesley W. Terpstra
2016-10-10 11:47:40 -07:00
parent 673cf1fdb5
commit a423f97844
2 changed files with 6 additions and 1 deletions
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6
src/main/scala/uncore/tilelink2/ToAXI4.scala
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@ -12,7 +12,11 @@ import scala.math.{min, max}
case class TLToAXI4Node(idBits: Int) extends MixedNode(TLImp, AXI4Imp)(
dFn = { case (1, _) =>
// We must erase all client information, because we crush their source Ids
Seq(AXI4MasterPortParameters(Seq(AXI4MasterParameters(id = IdRange(0, 1 << idBits)))))
val masters = Seq(
AXI4MasterParameters(
id = IdRange(0, 1 << idBits),
aligned = true))
Seq(AXI4MasterPortParameters(masters))
},
uFn = { case (1, Seq(AXI4SlavePortParameters(slaves, beatBytes))) =>
val managers = slaves.zipWithIndex.map { case (s, id) =>