riscv/rocket-chip
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.prm is output of chisel stage, not firrtl stage

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This commit is contained in:
Howard Mao 2016-06-28 17:34:37 -07:00
parent b30e0254ee
commit a39a0c0ec4
1 changed files with 2 additions and 2 deletions
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4
vsim/Makefrag-verilog
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@ -16,12 +16,12 @@ else
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(patsubst %.d,%.fir,$(notdir $@))) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL_JAR)
$(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR)
mkdir -p $(dir $@)
$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog