From a39a0c0ec4f09fb224d4b1e44ae6115ac52089f4 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 28 Jun 2016 17:34:37 -0700
Subject: [PATCH] .prm is output of chisel stage, not firrtl stage

---
 vsim/Makefrag-verilog | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index f50a902b..fc9158d7 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -16,12 +16,12 @@ else
 # files.
 .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
 
-$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d: $(chisel_srcs)
+$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs)
 	mkdir -p $(dir $@)
 	cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(patsubst %.d,%.fir,$(notdir $@))) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
 	mv $(generated_dir)/$(MODEL).fir $(generated_dir)/$(MODEL).$(CONFIG).fir
 
-$(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL_JAR)
+$(generated_dir)/%.v: $(generated_dir)/%.fir $(FIRRTL_JAR)
 	mkdir -p $(dir $@)
 	$(FIRRTL) $(patsubst %,-i %,$(filter %.fir,$^)) -o $@ -X verilog