riscv/rocket-chip
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Refactored packet headers/payloads

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This commit is contained in:
Henry Cook
2013-01-15 15:50:37 -08:00
parent e1225c5114
commit a2fa3fd04d
5 changed files with 51 additions and 50 deletions
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4
rocket/src/main/scala/tile.scala
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@ -34,7 +34,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
}
val core = new Core
val icache = new Frontend()(confIn.icache)
val icache = new Frontend()(confIn.icache, lnConf)
val dcache = new HellaCache
val arbiter = new MemArbiter(memPorts)
@ -51,7 +51,7 @@ class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Compon
io.tilelink.probe_rep_data <> dcache.io.mem.probe_rep_data
if (conf.vec) {
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co)) // 128 sets x 1 ways (8KB)
val vicache = new Frontend()(ICacheConfig(128, 1, conf.co), lnConf) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
core.io.vimem <> vicache.io.cpu
}