riscv/rocket-chip
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Simplify handling of CAUSE register

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This commit is contained in:
Andrew Waterman
2014-01-24 15:56:01 -08:00
parent a2be21361e
commit a1b7774f5d
4 changed files with 9 additions and 15 deletions
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6
rocket/src/main/scala/ctrl.scala
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@ -6,7 +6,7 @@ import uncore.constants.MemoryOpConstants._
import ALU._
import Util._
class CtrlDpathIO extends Bundle()
class CtrlDpathIO(implicit conf: RocketConfiguration) extends Bundle
{
// outputs to datapath
val sel_pc = UInt(OUTPUT, 3)
@ -42,7 +42,7 @@ class CtrlDpathIO extends Bundle()
// exception handling
val retire = Bool(OUTPUT)
val exception = Bool(OUTPUT)
val cause = UInt(OUTPUT, 6)
val cause = UInt(OUTPUT, conf.xprlen)
val badvaddr_wen = Bool(OUTPUT) // high for a load/store access fault
// inputs from datapath
val inst = Bits(INPUT, 32)
@ -395,7 +395,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
val id_reg_fence = Reg(init=Bool(false))
val sr = io.dpath.status
var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UInt(CAUSE_INTERRUPT+i)))
var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UInt(BigInt(1) << (conf.xprlen-1) | i)))
val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts)
val id_interrupt = io.dpath.status.ei && id_interrupt_unmasked