diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 6f7ca640..b58e94a3 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -59,10 +59,6 @@ trait ScalarOpConstants {
 
   val RA = UInt(1, 5)
 }
-
-trait InterruptConstants {
-  val CAUSE_INTERRUPT = 32
-}
  
 trait VectorOpConstants {
   val VEC_X = Bits("b??", 2).toUInt
diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala
index 8a20f137..f01e241f 100644
--- a/rocket/src/main/scala/ctrl.scala
+++ b/rocket/src/main/scala/ctrl.scala
@@ -6,7 +6,7 @@ import uncore.constants.MemoryOpConstants._
 import ALU._
 import Util._
 
-class CtrlDpathIO extends Bundle()
+class CtrlDpathIO(implicit conf: RocketConfiguration) extends Bundle
 {
   // outputs to datapath
   val sel_pc   = UInt(OUTPUT, 3)
@@ -42,7 +42,7 @@ class CtrlDpathIO extends Bundle()
   // exception handling
   val retire = Bool(OUTPUT)
   val exception = Bool(OUTPUT)
-  val cause    = UInt(OUTPUT, 6)
+  val cause    = UInt(OUTPUT, conf.xprlen)
   val badvaddr_wen = Bool(OUTPUT) // high for a load/store access fault
   // inputs from datapath
   val inst    = Bits(INPUT, 32)
@@ -395,7 +395,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
   val id_reg_fence = Reg(init=Bool(false))
 
   val sr = io.dpath.status
-  var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UInt(CAUSE_INTERRUPT+i)))
+  var id_interrupts = (0 until sr.ip.getWidth).map(i => (sr.im(i) && sr.ip(i), UInt(BigInt(1) << (conf.xprlen-1) | i)))
 
   val (id_interrupt_unmasked, id_interrupt_cause) = checkExceptions(id_interrupts)
   val id_interrupt = io.dpath.status.ei && id_interrupt_unmasked
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index a763c370..70e04ec6 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -99,13 +99,13 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
     val evec = UInt(OUTPUT, VADDR_BITS+1)
     val exception = Bool(INPUT)
     val retire = Bool(INPUT)
-    val cause = UInt(INPUT, 6)
+    val cause = UInt(INPUT, conf.xprlen)
     val badvaddr_wen = Bool(INPUT)
     val pc = UInt(INPUT, VADDR_BITS+1)
     val sret = Bool(INPUT)
     val fatc = Bool(OUTPUT)
     val replay = Bool(OUTPUT)
-    val time = UInt(OUTPUT, 64)
+    val time = UInt(OUTPUT, conf.xprlen)
     val fcsr_rm = Bits(OUTPUT, FPConstants.RM_SZ)
     val fcsr_flags = Valid(Bits(width = FPConstants.FLAGS_SZ)).flip
   }
@@ -114,7 +114,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
   val reg_badvaddr = Reg(Bits(width = VADDR_BITS))
   val reg_evec = Reg(Bits(width = VADDR_BITS))
   val reg_compare = Reg(Bits(width = 32))
-  val reg_cause = Reg(Bits(width = io.cause.getWidth))
+  val reg_cause = Reg(Bits(width = conf.xprlen))
   val reg_tohost = Reg(init=Bits(0, conf.xprlen))
   val reg_fromhost = Reg(init=Bits(0, conf.xprlen))
   val reg_sup0 = Reg(Bits(width = conf.xprlen))
@@ -122,8 +122,8 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
   val reg_ptbr = Reg(UInt(width = PADDR_BITS))
   val reg_stats = Reg(init=Bool(false))
   val reg_status = Reg(new Status) // reset down below
-  val reg_time = WideCounter(64)
-  val reg_instret = WideCounter(64, io.retire)
+  val reg_time = WideCounter(conf.xprlen)
+  val reg_instret = WideCounter(conf.xprlen, io.retire)
   val reg_fflags = Reg(UInt(width = 5))
   val reg_frm = Reg(UInt(width = 3))
 
@@ -208,7 +208,6 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
 
   val read_impl = Bits(2)
   val read_ptbr = reg_ptbr(PADDR_BITS-1,PGIDX_BITS) << PGIDX_BITS
-  val read_cause = reg_cause(reg_cause.getWidth-1) << conf.xprlen-1 | reg_cause(reg_cause.getWidth-2,0)
 
   val read_mapping = Map[Int,Bits](
     CSRs.fflags -> (if (conf.fpu) reg_fflags else UInt(0)),
@@ -226,7 +225,7 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
     CSRs.count -> reg_time,
     CSRs.compare -> reg_compare,
     CSRs.evec -> reg_evec,
-    CSRs.cause -> read_cause,
+    CSRs.cause -> reg_cause,
     CSRs.status -> io.status.toBits,
     CSRs.hartid -> io.host.id,
     CSRs.impl -> read_impl,
diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala
index ca2926fc..0fcb6580 100644
--- a/rocket/src/main/scala/package.scala
+++ b/rocket/src/main/scala/package.scala
@@ -1,6 +1,5 @@
 package object rocket extends 
   rocket.constants.ScalarOpConstants with
-  rocket.constants.InterruptConstants with 
   rocket.constants.VectorOpConstants
 {
   val START_ADDR = 0x2000