riscv/rocket-chip
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make ZscaleChip work with new parameters framework

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This commit is contained in:
Yunsup Lee 2015-10-25 10:24:39 -07:00
parent c3a7dcf0ab
commit a175afae73
6 changed files with 27 additions and 32 deletions
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2
Makefrag
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@ -3,7 +3,7 @@ ifndef RISCV
$(error Please set environment variable RISCV. Please take a look at README)
endif
MODEL := Top
MODEL ?= Top
PROJECT := rocketchip
CXX ?= g++
CXXFLAGS := -O1

2
rocket

@ -1 +1 @@
Subproject commit 884ceddaa034376be7e10f2446c4e33618a9d190
Subproject commit e31be75a6a6d2ff0334fc1f9ce9c4730281bd09a

4
src/main/scala/Configs.scala
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@ -26,7 +26,6 @@ class DefaultConfig extends Config (
new AddrMap(csrs :+ scr)
}
pname match {
case UseZscale => false
case HtifKey => HtifParameters(
width = Dump("HTIF_WIDTH", 16),
nSCR = 64,
@ -225,9 +224,8 @@ class WithZscale extends Config(
case BuildZscale => {
TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
TestGeneration.addSuites(List(zscaleBmarks))
(r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1toL2"})))
(r: Bool, p: Parameters) => Module(new Zscale(r)(p))
}
case UseZscale => true
case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
}

6
src/main/scala/RocketChip.scala
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@ -81,7 +81,7 @@ class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
implicit val p = topParams
val io = new TopIO
if(!p(UseZscale)) {
val temp = Module(new MultiChannelTop)
val arb = Module(new NastiArbiter(nMemChannels))
val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
@ -96,10 +96,6 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
// tie off the mmio port
val errslave = Module(new NastiErrorSlave)
errslave.io <> temp.io.mmio
} else {
val temp = Module(new ZscaleTop)
io.host <> temp.io.host
}
}
class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {

3
src/main/scala/ZscaleChip.scala
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@ -61,7 +61,8 @@ class ZscaleSystem(implicit p: Parameters) extends Module {
io.corereset <> pbus.io.slaves(1)
}
class ZscaleTop(implicit p: Parameters) extends Module {
class ZscaleTop(topParams: Parameters) extends Module {
implicit val p = topParams.alterPartial({case TLId => "L1toL2" })
val io = new Bundle {
val host = new HtifIO
}

16
vsrc/ZscaleTestHarness.v
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@ -18,14 +18,14 @@ module ZscaleTestHarness;
.io_host_reset(reset),
.io_host_id(1'd0),
.io_host_pcr_req_ready(),
.io_host_pcr_req_valid(1'b1),
.io_host_pcr_req_bits_rw(1'b0),
.io_host_pcr_req_bits_addr(12'h780), // tohost register
.io_host_pcr_req_bits_data({dummy, 32'd0}),
.io_host_pcr_rep_ready(1'b1),
.io_host_pcr_rep_valid(csr_resp_valid),
.io_host_pcr_rep_bits({dummy, csr_resp_bits}),
.io_host_csr_req_ready(),
.io_host_csr_req_valid(1'b1),
.io_host_csr_req_bits_rw(1'b0),
.io_host_csr_req_bits_addr(12'h780), // tohost register
.io_host_csr_req_bits_data({dummy, 32'd0}),
.io_host_csr_resp_ready(1'b1),
.io_host_csr_resp_valid(csr_resp_valid),
.io_host_csr_resp_bits({dummy, csr_resp_bits}),
.io_host_ipi_req_ready(1'b1),
.io_host_ipi_req_valid(),