From a175afae73d83e7a06b35de9b304bab0f3594bb5 Mon Sep 17 00:00:00 2001
From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Sun, 25 Oct 2015 10:24:39 -0700
Subject: [PATCH] make ZscaleChip work with new parameters framework

---
 Makefrag                        |  2 +-
 rocket                          |  2 +-
 src/main/scala/Configs.scala    |  4 +---
 src/main/scala/RocketChip.scala | 32 ++++++++++++++------------------
 src/main/scala/ZscaleChip.scala |  3 ++-
 vsrc/ZscaleTestHarness.v        | 16 ++++++++--------
 6 files changed, 27 insertions(+), 32 deletions(-)

diff --git a/Makefrag b/Makefrag
index 5019032b..57fb8465 100644
--- a/Makefrag
+++ b/Makefrag
@@ -3,7 +3,7 @@ ifndef RISCV
 $(error Please set environment variable RISCV. Please take a look at README)
 endif
 
-MODEL := Top
+MODEL ?= Top
 PROJECT := rocketchip
 CXX ?= g++
 CXXFLAGS := -O1
diff --git a/rocket b/rocket
index 884cedda..e31be75a 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 884ceddaa034376be7e10f2446c4e33618a9d190
+Subproject commit e31be75a6a6d2ff0334fc1f9ce9c4730281bd09a
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index 9828ee29..7589db45 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -26,7 +26,6 @@ class DefaultConfig extends Config (
       new AddrMap(csrs :+ scr)
     }
     pname match {
-      case UseZscale => false
       case HtifKey => HtifParameters(
                        width = Dump("HTIF_WIDTH", 16),
                        nSCR = 64,
@@ -225,9 +224,8 @@ class WithZscale extends Config(
     case BuildZscale => {
       TestGeneration.addSuites(List(rv32ui("p"), rv32um("p")))
       TestGeneration.addSuites(List(zscaleBmarks))
-      (r: Bool, p: Parameters) => Module(new Zscale(r)(p.alterPartial({case TLId => "L1toL2"})))
+      (r: Bool, p: Parameters) => Module(new Zscale(r)(p))
     }
-    case UseZscale => true
     case BootROMCapacity => Dump("BOOT_CAPACITY", 16*1024)
     case DRAMCapacity => Dump("DRAM_CAPACITY", 64*1024*1024)
   }
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 879f6adf..49dd0c47 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -81,25 +81,21 @@ class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
 class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   implicit val p = topParams
   val io = new TopIO
-  if(!p(UseZscale)) {
-    val temp = Module(new MultiChannelTop)
-    val arb = Module(new NastiArbiter(nMemChannels))
-    val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
-    arb.io.master <> temp.io.mem
-    conv.io.nasti <> arb.io.slave
-    io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
-    io.mem.req_data <> Queue(conv.io.mem.req_data, mifDataBeats)
-    conv.io.mem.resp <> Queue(io.mem.resp, mifDataBeats)
-    io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
-    io.host <> temp.io.host
 
-    // tie off the mmio port
-    val errslave = Module(new NastiErrorSlave)
-    errslave.io <> temp.io.mmio
-  } else {
-    val temp = Module(new ZscaleTop)
-    io.host <> temp.io.host
-  }
+  val temp = Module(new MultiChannelTop)
+  val arb = Module(new NastiArbiter(nMemChannels))
+  val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
+  arb.io.master <> temp.io.mem
+  conv.io.nasti <> arb.io.slave
+  io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
+  io.mem.req_data <> Queue(conv.io.mem.req_data, mifDataBeats)
+  conv.io.mem.resp <> Queue(io.mem.resp, mifDataBeats)
+  io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
+  io.host <> temp.io.host
+
+  // tie off the mmio port
+  val errslave = Module(new NastiErrorSlave)
+  errslave.io <> temp.io.mmio
 }
 
 class MultiChannelTop(implicit val p: Parameters) extends Module with HasTopLevelParameters {
diff --git a/src/main/scala/ZscaleChip.scala b/src/main/scala/ZscaleChip.scala
index b555c4a7..5b53164f 100644
--- a/src/main/scala/ZscaleChip.scala
+++ b/src/main/scala/ZscaleChip.scala
@@ -61,7 +61,8 @@ class ZscaleSystem(implicit p: Parameters)  extends Module {
   io.corereset <> pbus.io.slaves(1)
 }
 
-class ZscaleTop(implicit p: Parameters) extends Module {
+class ZscaleTop(topParams: Parameters) extends Module {
+  implicit val p = topParams.alterPartial({case TLId => "L1toL2" })
   val io = new Bundle {
     val host = new HtifIO
   }
diff --git a/vsrc/ZscaleTestHarness.v b/vsrc/ZscaleTestHarness.v
index f1a944d6..c9d7e5a2 100644
--- a/vsrc/ZscaleTestHarness.v
+++ b/vsrc/ZscaleTestHarness.v
@@ -18,14 +18,14 @@ module ZscaleTestHarness;
     .io_host_reset(reset),
 
     .io_host_id(1'd0),
-    .io_host_pcr_req_ready(),
-    .io_host_pcr_req_valid(1'b1),
-    .io_host_pcr_req_bits_rw(1'b0),
-    .io_host_pcr_req_bits_addr(12'h780), // tohost register
-    .io_host_pcr_req_bits_data({dummy, 32'd0}),
-    .io_host_pcr_rep_ready(1'b1),
-    .io_host_pcr_rep_valid(csr_resp_valid),
-    .io_host_pcr_rep_bits({dummy, csr_resp_bits}),
+    .io_host_csr_req_ready(),
+    .io_host_csr_req_valid(1'b1),
+    .io_host_csr_req_bits_rw(1'b0),
+    .io_host_csr_req_bits_addr(12'h780), // tohost register
+    .io_host_csr_req_bits_data({dummy, 32'd0}),
+    .io_host_csr_resp_ready(1'b1),
+    .io_host_csr_resp_valid(csr_resp_valid),
+    .io_host_csr_resp_bits({dummy, csr_resp_bits}),
     
     .io_host_ipi_req_ready(1'b1),
     .io_host_ipi_req_valid(),