riscv/rocket-chip
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rocketchip: cut coreplex from rocketchip

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This commit is contained in:
Wesley W. Terpstra
2016-11-22 15:01:45 -08:00
parent c80ee06472
commit a140b07009
7 changed files with 69 additions and 58 deletions
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21
src/main/scala/rocketchip/Periphery.scala
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@ -71,16 +71,17 @@ trait PeripheryExtInterruptsModule {
/////
trait PeripheryMasterAXI4Mem {
this: BaseTop[BaseCoreplex] with TopNetwork =>
this: TopNetwork =>
val module: PeripheryMasterAXI4MemModule
private val config = p(ExtMem)
private val channels = coreplexMem.size
private val channels = p(BankedL2Config).nMemoryChannels
val mem_axi4 = coreplexMem.zipWithIndex.map { case (node, i) =>
val mem_axi4 = Seq.tabulate(channels) { i =>
val c_size = config.size/channels
val c_base = config.base + c_size*i
val axi4 = AXI4BlindOutputNode(AXI4SlavePortParameters(
AXI4BlindOutputNode(AXI4SlavePortParameters(
slaves = Seq(AXI4SlaveParameters(
address = List(AddressSet(c_base, c_size-1)),
regionType = RegionType.UNCACHED, // cacheable
@ -89,14 +90,12 @@ trait PeripheryMasterAXI4Mem {
supportsRead = TransferSizes(1, 256),
interleavedId = Some(0))), // slave does not interleave read responses
beatBytes = config.beatBytes))
}
axi4 :=
// AXI4Fragmenter(lite=false, maxInFlight = 20)( // beef device up to support awlen = 0xff
TLToAXI4(idBits = config.idBits)( // use idBits = 0 for AXI4-Lite
TLWidthWidget(coreplex.l1tol2_beatBytes)( // convert width before attaching to the l1tol2
node))
axi4
val mem = mem_axi4.map { node =>
val foo = LazyModule(new TLToAXI4(config.idBits))
node := foo.node
foo.node
}
}